KR970053981A - 메모리 셀 및 그 구조 제조 방법 - Google Patents

메모리 셀 및 그 구조 제조 방법 Download PDF

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KR970053981A
KR970053981A KR1019960046027A KR19960046027A KR970053981A KR 970053981 A KR970053981 A KR 970053981A KR 1019960046027 A KR1019960046027 A KR 1019960046027A KR 19960046027 A KR19960046027 A KR 19960046027A KR 970053981 A KR970053981 A KR 970053981A
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KR1019960046027A
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KR100265081B1 (ko
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존 케이 데브로쎄
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포만 제프리 엘
인터내셔널 비지네스 머신즈 코포레이션
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/907—Folded bit line dram configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

8제곱 배 비트 라인(eight square folded bit line)동적 랜덤 액세스 메모리(DRAM) 셀용 셀 레이아웃, 셀구조, 및 프로세스 시퀸스가 두개의 피소그래피적 형상의 전송 장치 채널 길이를 허용한다. 프로세서 시퀸스가 딥 트렌치 칼라나 캡침착의 제거, 떠는 위드 라인간 캐패시턴스의 감소를 허용할 수도 있다. 이 방법에 의해 준비된 셀이 8제곱 배 비트 라인 DRAM 셀내에 두개의 리소그래피적 형상 전송 장치 채널 길이를 허용한다.
이 방법은 형상이 결정되지 않은 스페이서를 갖는 종래의 프로세싱 기법을 사용하며 종래의 구조를 사용한다.
이 셀은 단지 한개의 부가적 마스크(GPC)와 최소의 부가적 프로세싱을 요구한다. 프로세스 시퀸스는 딥 트렌치(DT) 프로세싱으로 부터 시작하여 SiO2침착, 평탄화 및 패드 스트립으로 이어진다. 이어서, 게이트 SiO2폴리실리콘, 및 패드가 침착된다. 구조가 얕은 트렌치 절연 마스크를 사용하여 에칭되어 SiO2로 채워진다. 평탄화 후, 절연체가 얇게 침착되고 구조가 다시 게이트 폴리 접촉 미스크로 에칭된다. 이어서, 게이트 전도데가 침착된다. 최종 에칭 후, 와이어링이 더해진다.

Description

메모리 셀 및 그 구조 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제9도는 스페이서, 정션, 패시케이션, 접촉 및 와이어링 후의 셀 구조에 대한 단면도.

Claims (5)

  1. 8제곱 배 비트 라인 동적 랜덤 액세스 메모리내에 두개의 리소그래픽적 형상의 평면 전송 장치 채널 길이를 갖는 메모리 셀.
  2. 메모리 셀 구조체를 제조하는 방법에 있어서, 트렌치, 절연 영역 및 게이트 SiO2와 게이트 폴리 실리콘으로 덮힌 활성 지역영역을 갖도록 제조도니 셀을 제공하는 단계와 절연체 박 층을 제공하는 단계와 게이트 폴리실리콘 접촉 마스크로 상기 절연체를 에칭하는 단계와 게이트 전도체와 게이트 전동체 캡을 침착하는 단계와 게이트 전도체 마스크로 상기 게이트SiO2상에 중단되하는 상기 게이트 전도체 캡, 게이트 전도체 및 게이트 폴리실리콘을 에칭하는 단계와 스페이서, 정션, 패시베이션, 접촉부, 와이어링을 더하는 단계를 포함하는 메모리 셀 구조 제조 방법.
  3. 제2항에 있어서, 프로세싱용 셀을 제공하는 상기 단계는 SiO2게이트 폴리실리콘 및, 패드를 상기 셀상에 침착하는 단계와 상기 셀을 딥 트렌치 프로세싱하느 단계와 샐로우 트렌치 절연 마스크를 사용하여 에칭하는 단계와 SiO2필을 침착하는 평탄화하는 단계를 포함하는 메모리 셀 구조 제조 방법.
  4. 제2항에 있어서, 프로세싱용 셀을 제공하는 상기 단계는 딥 트렌치 프로세싱으로 제조된 셀을 제공하는 단계와 샐로우 드렌치 절연 마스크로 상기 셀을 에칭하는 단계와 SiO2필을 침착하는 단계와 게이트 폴리실리콘의 바람직한 높은 레벨로 상기 SiO2필을 평탄화하는 단계와 게이트 SiO2및 게이트 폴리실리콘을 침착하는 단계와 상기 게이트 폴리실리콘을 상기 바람직한 높이로 평탄화하느 단계를 포함하는 메모리 셀 구조 제조 방법.
  5. 제2항에 있어서, 프로세싱용 셀을 제공하는 상기 단계는 딥 트렌치 프로세싱으로 제조된 셀을 제공하는 단계와 트렌치 캡을 침착하여 평탄화하느 ㄴ단계와 게이트 SiO2및 게이트 폴리실리콘을 침착하는 단계와 샐로우트렌치 절연 마스클르 사용하여 에칭하는 단계와 SiO2필을 침착하게 평탄화하는 단계를 포함하는 메모리 셀 구조 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960046027A 1995-12-20 1996-10-15 메모리 셀 및 그 구조체 제조 방법 KR100265081B1 (ko)

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US8/575,311 1995-12-20
US08/575,311 1995-12-20
US08/575,311 US5614431A (en) 1995-12-20 1995-12-20 Method of making buried strap trench cell yielding an extended transistor

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KR100265081B1 KR100265081B1 (ko) 2000-09-01

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KR100265081B1 (ko) 2000-09-01
US5614431A (en) 1997-03-25
EP0780895A3 (en) 1999-06-16
EP0780895A2 (en) 1997-06-25
US5874758A (en) 1999-02-23
JPH09199688A (ja) 1997-07-31
JP3640486B2 (ja) 2005-04-20

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