KR970003887A - 반도체 패키지 - Google Patents

반도체 패키지 Download PDF

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Publication number
KR970003887A
KR970003887A KR1019950017069A KR19950017069A KR970003887A KR 970003887 A KR970003887 A KR 970003887A KR 1019950017069 A KR1019950017069 A KR 1019950017069A KR 19950017069 A KR19950017069 A KR 19950017069A KR 970003887 A KR970003887 A KR 970003887A
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KR
South Korea
Prior art keywords
semiconductor package
package
paddle
semiconductor
semiconductor chip
Prior art date
Application number
KR1019950017069A
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English (en)
Other versions
KR0152948B1 (ko
Inventor
장현성
김진섭
Original Assignee
문정환
Lg 반도체주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 문정환, Lg 반도체주식회사 filed Critical 문정환
Priority to KR1019950017069A priority Critical patent/KR0152948B1/ko
Publication of KR970003887A publication Critical patent/KR970003887A/ko
Application granted granted Critical
Publication of KR0152948B1 publication Critical patent/KR0152948B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

본 발명은 반도체 패키지에 관한 것으로, 종래 반도체 패키지는 열 방출이 잘되도록 패키지의 하부에 히트-싱크를 부착하였으나 자재비 및 설치공정에 따른 생산비가 상승하는 문제점이 있었던 바, 본 발명은 패들(10)의 상부에 반도체 칩(11)이 부착되어 있고, 그 반도체 칩(11)의 상부에 형성된 칩 패드(11a)와 리드 프레임(12)이 인너 리드(12a)가 금속 와이어(13)로 연결되어 있으며, 상기 반도체 칩(11)과 인너 리드(12a)를 포함하는 일정면적이 에폭시로 몰딩되는 이엠시(14)로구성되어 있는 반도체 패키지에 있어서, 상기 패들(10)을 연장형성하고, 그 연장형성된 패들(10)이 이엠시(14)의 하면에설치되도록 하여 패키지 작동시 외부로의 열방출 경로가 되도록 함으로써 히트-싱크를 배제하는데 따른 생산비의 절감효과가 있는 것이다.

Description

반도체 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 의한 반도체 패키지의 구성을 보인 종단면도, 제4도는 본 발명에 의한 반도체 패키지의 패들이 외부에 노출된 상태를 보인 저면도.

Claims (1)

  1. 패들의 상부에 반도체 칩이 부착되어 있고, 그 반도체 칩의 상부에 형성된 칩 패드와 리드 프레임의 인너리드가 금속 와이어로 연결되어 있으며, 상기 반도체 칩과 인너 리드를 포함하는 일정면적이 에폭시로 몰딩되는 이엠시로구성되어 있는 반도체 패키지에 있어서, 상기 패들을 연장형성하고, 그 연장형성된 패들이 이엠시의 하면에 설치되도록하여 패키지 작동시 외부로의 열방출 경로가 되도록 한 것을 특징으로 하는 반도체 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950017069A 1995-06-23 1995-06-23 반도체 패키지 KR0152948B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950017069A KR0152948B1 (ko) 1995-06-23 1995-06-23 반도체 패키지

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950017069A KR0152948B1 (ko) 1995-06-23 1995-06-23 반도체 패키지

Publications (2)

Publication Number Publication Date
KR970003887A true KR970003887A (ko) 1997-01-29
KR0152948B1 KR0152948B1 (ko) 1998-10-01

Family

ID=19417997

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950017069A KR0152948B1 (ko) 1995-06-23 1995-06-23 반도체 패키지

Country Status (1)

Country Link
KR (1) KR0152948B1 (ko)

Also Published As

Publication number Publication date
KR0152948B1 (ko) 1998-10-01

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