KR960705409A - 폴딩 스테이지 및 폴딩 아날로그-투-디지탈 변환기(Folding stage and folding analog-to-digital converter) - Google Patents

폴딩 스테이지 및 폴딩 아날로그-투-디지탈 변환기(Folding stage and folding analog-to-digital converter)

Info

Publication number
KR960705409A
KR960705409A KR1019960701105A KR19960701105A KR960705409A KR 960705409 A KR960705409 A KR 960705409A KR 1019960701105 A KR1019960701105 A KR 1019960701105A KR 19960701105 A KR19960701105 A KR 19960701105A KR 960705409 A KR960705409 A KR 960705409A
Authority
KR
South Korea
Prior art keywords
node
folding
output
transistor
summing node
Prior art date
Application number
KR1019960701105A
Other languages
English (en)
Korean (ko)
Inventor
브람 나우타
아놀두스 게라르두스 빌헬무스 베네스
Original Assignee
요트.게.아. 롤페즈
필립스 일렉트로닉스 엔.브이.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 요트.게.아. 롤페즈, 필립스 일렉트로닉스 엔.브이. filed Critical 요트.게.아. 롤페즈
Publication of KR960705409A publication Critical patent/KR960705409A/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/20—Increasing resolution using an n bit system to obtain n + m bits
    • H03M1/202—Increasing resolution using an n bit system to obtain n + m bits by interpolation
    • H03M1/203—Increasing resolution using an n bit system to obtain n + m bits by interpolation using an analogue interpolation circuit
    • H03M1/204—Increasing resolution using an n bit system to obtain n + m bits by interpolation using an analogue interpolation circuit in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators
    • H03M1/205—Increasing resolution using an n bit system to obtain n + m bits by interpolation using an analogue interpolation circuit in which one or more virtual intermediate reference signals are generated between adjacent original reference signals, e.g. by connecting pre-amplifier outputs to multiple comparators using resistor strings for redistribution of the original reference signals or signals derived therefrom
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/141—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit in which at least one step is of the folding type; Folding stages therefore
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0602—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic
    • H03M1/0604—Continuously compensating for, or preventing, undesired influence of physical parameters of deviations from the desired transfer characteristic at one point, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/0607—Offset or drift compensation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
KR1019960701105A 1994-07-07 1995-06-27 폴딩 스테이지 및 폴딩 아날로그-투-디지탈 변환기(Folding stage and folding analog-to-digital converter) KR960705409A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP94201957 1994-07-07
EP94201957.1 1994-07-07
PCT/IB1995/000520 WO1996002088A1 (en) 1994-07-07 1995-06-27 Folding stage and folding analog-to-digital converter

Publications (1)

Publication Number Publication Date
KR960705409A true KR960705409A (ko) 1996-10-09

Family

ID=8217017

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960701105A KR960705409A (ko) 1994-07-07 1995-06-27 폴딩 스테이지 및 폴딩 아날로그-투-디지탈 변환기(Folding stage and folding analog-to-digital converter)

Country Status (5)

Country Link
US (1) US5640163A (ja)
EP (1) EP0722633A1 (ja)
JP (1) JP3555956B2 (ja)
KR (1) KR960705409A (ja)
WO (1) WO1996002088A1 (ja)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3795923B2 (ja) * 1995-09-08 2006-07-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ サンプリングによる信号処理
CN1169217A (zh) * 1995-09-08 1997-12-31 菲利浦电子有限公司 具有折叠和内插的模/数变换
SG71140A1 (en) * 1997-08-15 2000-03-21 Texas Instruments Inc Differential pair-based folding interpolator circuit for an analog-to-digital converter
ATE283579T1 (de) * 2000-02-14 2004-12-15 Koninkl Philips Electronics Nv Strom-spannungsumwandler mit steuerbarer verstärkung und signalverarbeitender schaltkreis mit einem solchen umwandler
US7009547B2 (en) * 2001-12-17 2006-03-07 University Of Utah Research Foundation Current steering folding circuit
US6762706B2 (en) * 2002-06-12 2004-07-13 Freescale Semiconductor, Inc. Reduced power analog-to-digital converter and method thereof
US7620116B2 (en) * 2003-02-28 2009-11-17 Rambus Inc. Technique for determining an optimal transition-limiting code for use in a multi-level signaling system
US6917312B2 (en) * 2003-11-10 2005-07-12 Rambus Inc. Technique for improving the quality of digital signals in a multi-level signaling system
US7236115B1 (en) * 2004-01-22 2007-06-26 National Semiconductor Corporation Distributed current sources for folding ADC amplifier stages
US20060126751A1 (en) * 2004-12-10 2006-06-15 Anthony Bessios Technique for disparity bounding coding in a multi-level signaling system
TWI346451B (en) * 2008-02-20 2011-08-01 Novatek Microelectronics Corp Amplification circuits with function of voltage interpolation
CN101527549B (zh) * 2008-03-04 2011-04-13 联咏科技股份有限公司 具电压内插功能的放大器电路
FR2929777B1 (fr) * 2008-04-04 2010-04-23 E2V Semiconductors Convertisseur analogique-numerique rapide a structure de repliement de signal amelioree par reduction du nombre de cellules elementaires
US7839317B1 (en) 2009-07-13 2010-11-23 Don Roy Sauer Folding comparator compatible with level-crossing sampling
US8674869B2 (en) 2010-01-22 2014-03-18 Nec Corporation A/D conversion circuit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4386339A (en) * 1980-03-31 1983-05-31 Hewlett-Packard Company Direct flash analog-to-digital converter and method
US5126742A (en) * 1990-11-06 1992-06-30 Signal Processing Technologies, Inc. Analog to digital converter with double folding interpolation circuitry
US5070332A (en) * 1991-03-18 1991-12-03 Burr-Brown Corporation Two-step subranging analog to digital converter
US5376937A (en) * 1993-02-22 1994-12-27 The Regents Of The University Of California Folding circuit

Also Published As

Publication number Publication date
JPH09502856A (ja) 1997-03-18
JP3555956B2 (ja) 2004-08-18
EP0722633A1 (en) 1996-07-24
US5640163A (en) 1997-06-17
WO1996002088A1 (en) 1996-01-25

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E601 Decision to refuse application