KR960036039A - Esd 보호 기능을 갖는 cmos 구조의 제조 방법 - Google Patents

Esd 보호 기능을 갖는 cmos 구조의 제조 방법 Download PDF

Info

Publication number
KR960036039A
KR960036039A KR1019960007825A KR19960007825A KR960036039A KR 960036039 A KR960036039 A KR 960036039A KR 1019960007825 A KR1019960007825 A KR 1019960007825A KR 19960007825 A KR19960007825 A KR 19960007825A KR 960036039 A KR960036039 A KR 960036039A
Authority
KR
South Korea
Prior art keywords
region
oxide film
conductivity type
protective oxide
gate
Prior art date
Application number
KR1019960007825A
Other languages
English (en)
Inventor
빌름스메이어 클라우스
Original Assignee
레오노레 흐르니크
도이취 아이티티 인더스트리스 게젤샤프트 미트 베쉬랭크터 하프퉁
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 레오노레 흐르니크, 도이취 아이티티 인더스트리스 게젤샤프트 미트 베쉬랭크터 하프퉁 filed Critical 레오노레 흐르니크
Publication of KR960036039A publication Critical patent/KR960036039A/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/934—Sheet resistance, i.e. dopant parameters

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

ESD 보호 기능을 갖는 CMOS 구조의 제조 방법을 제공한다. 외부 트랜지스터는 필드 산화막 영역(6) 및 게이트 영역(8)에 인접한 각 소스 및 드레인 영역(10, 11)의 구역을 커버하기 위해 마스크된 보호 산화막 층(13)으로 덮혀 있다. 그런 다음 보호 산화막 층(13)은 규산화 공정이 이루어진 후 열처리된다.

Description

ESD 보호 기능을 갖는 CMOS 구조의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 보호 산화막 층의 에칭 후에 본 발명에 따른 방법에 의해서 제조된 CMOS 구조의 일실시에를 나타내는 도면.

Claims (4)

  1. 제1도전성 타입의 기판(5)에 상기 제1도전성 타입에 반대되는 제2도전성 타입의 적어도 하나의 웰영역(3, 4)을 형성하는 단계와; 필드 산화막 영역(6) 및 게이트 산화막 영역(8)을 형성하는 단계와; 상기 기판(5)에서는 제2도전성 타입이고 웰 영역(3, 4)에서는 제1도전성 타입이며 각각의 게이트 산화막 영역(8)과 연결된 소스 및 드레인 영역(10, 11)을 형성하는 단계와; 상기 필드 산화막 영역(6) 및 게이트 영역(8)에 인접한 외부 트랜지스터(7)의 각 소스 및 드레인 영역(10, 11)의 구역을 커버하기 위해 마스크되는 보호 산화막 층(13)을 증착시키는 단계와; 상기 보호 산화막 층(13)이 제공된 구조를 규산화하는 단계를 포함하는 ESD 보호(정전 방전에 대한 보호) 기능을 갖는 CMOS 구조의 제조 방법에 있어서, 상기 보호 산화막 층(13)은 상기 필드 산화막 영역(6) 및 게이트 영역(8)에 인접한 공간(12)보다 더 큰 에칭률을 가지며, 규산화 처리 이전에 보호 산화막 층(13)의 에칭률을 감소시키도록 파라미터가 선택되는 열처리를 받는 것을 특징으로 하는 ESD 보호 기능을 갖는 COMS 구조의 제조 방법.
  2. 제1항에 있어서, 상기 열처리로서 펄스 어닐링 공정이 온도 800도와 900도 사이에서, 바람직하게는 875도에서 20초 내지 5분 간격, 바람직하게는 3분 간격으로 수행되는 것을 특지으로 하는 ESD 보호 기능을 갖는 CMOS 구조의 제조 방법.
  3. 제1항 또는 제2항에 있어서, 상기 열처리 이전에, 보호 산화막 층(13)의 에칭률에 대한 필드 산화막 영역 및 공간의 에칭률의 비는 20:1인 것을 특징으로 하는 ESD 보호 기능을 갖는 CMOS 구조의 제조 방법.
  4. 제1항 내지 제3항중 어느 한 항에 있어서, 상기 보호 산화막 층(13)의 두께는 200Å 보다 큰 것을 특징으로 하는 ESD 보호 기능을 갖는 CMOS 구조의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960007825A 1995-03-24 1996-03-22 Esd 보호 기능을 갖는 cmos 구조의 제조 방법 KR960036039A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19510777.2 1995-03-24
DE19510777A DE19510777C1 (de) 1995-03-24 1995-03-24 Verfahren zum Herstellen einer CMOS-Struktur mit ESD-Schutz

Publications (1)

Publication Number Publication Date
KR960036039A true KR960036039A (ko) 1996-10-28

Family

ID=7757606

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960007825A KR960036039A (ko) 1995-03-24 1996-03-22 Esd 보호 기능을 갖는 cmos 구조의 제조 방법

Country Status (5)

Country Link
US (1) US5620920A (ko)
EP (1) EP0734067A3 (ko)
JP (1) JPH08279565A (ko)
KR (1) KR960036039A (ko)
DE (1) DE19510777C1 (ko)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5744839A (en) * 1996-06-11 1998-04-28 Micron Technology, Inc. ESD protection using selective siliciding techniques
JPH1070266A (ja) * 1996-08-26 1998-03-10 Nec Corp 半導体装置およびその製造方法
JPH1168103A (ja) * 1997-08-22 1999-03-09 Mitsubishi Electric Corp 半導体装置の製造方法
US5897348A (en) * 1998-03-13 1999-04-27 Texas Instruments - Acer Incorporated Low mask count self-aligned silicided CMOS transistors with a high electrostatic discharge resistance
TW437052B (en) * 1998-03-30 2001-05-28 United Microelectronics Corp Manufacturing method for electrostatic protection circuit with reduced photomask processing
FR2779574B1 (fr) 1998-06-03 2003-01-31 Sgs Thomson Microelectronics Procede de fabrication de transistors haute et basse tension
US6337340B1 (en) 1998-08-14 2002-01-08 Gpi Nil Holdings, Inc. Carboxylic acids and isosteres of heterocyclic ring compounds having multiple heteroatoms for vision and memory disorders
US6110771A (en) * 1998-09-11 2000-08-29 Lg Semicon Co., Ltd. Fabrication method of a semiconductor device using self-aligned silicide CMOS having a dummy gate electrode
JP4068746B2 (ja) * 1998-12-25 2008-03-26 株式会社ルネサステクノロジ 半導体集積回路装置
US6121092A (en) * 1999-02-02 2000-09-19 Macronix International Co., Ltd. Silicide blocking process to form non-silicided regions on MOS devices
US6063672A (en) * 1999-02-05 2000-05-16 Lsi Logic Corporation NMOS electrostatic discharge protection device and method for CMOS integrated circuit
DE19953889C2 (de) * 1999-11-09 2002-02-07 Infineon Technologies Ag Schaltungsanordnung zur Gebührenimpulserkennung
DE19957533A1 (de) * 1999-11-30 2001-06-07 Infineon Technologies Ag Halbleiterschaltungsanordnung und Verfahren zur Herstellung
US6587320B1 (en) 2000-01-04 2003-07-01 Sarnoff Corporation Apparatus for current ballasting ESD sensitive devices
KR100447230B1 (ko) * 2001-12-22 2004-09-04 주식회사 하이닉스반도체 반도체 소자의 살리사이드 형성 방법
US7010208B1 (en) * 2002-06-24 2006-03-07 Luxtera, Inc. CMOS process silicon waveguides
US20060286756A1 (en) * 2005-06-20 2006-12-21 Chien-Wei Chen Semiconductor process and method for reducing parasitic capacitance
US7368948B2 (en) * 2005-07-15 2008-05-06 Infineon Technologies Ag Integrated receiver circuit
JP2006203225A (ja) * 2006-02-22 2006-08-03 Renesas Technology Corp 半導体集積回路装置の製造方法
US7682890B2 (en) * 2006-08-18 2010-03-23 United Microelectronics Corp. Method of fabricating semiconductor device
US7439134B1 (en) * 2007-04-20 2008-10-21 Freescale Semiconductor, Inc. Method for process integration of non-volatile memory cell transistors with transistors of another type
JP2011071329A (ja) * 2009-09-25 2011-04-07 Seiko Instruments Inc 半導体装置
US8603908B2 (en) * 2011-05-06 2013-12-10 Lam Research Corporation Mitigation of silicide formation on wafer bevel

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139058A (ja) * 1984-12-11 1986-06-26 Seiko Epson Corp 半導体製造装置
US5247199A (en) * 1986-01-15 1993-09-21 Harris Corporation Process for forming twin well CMOS integrated circuits
IT1213027B (it) * 1986-01-24 1989-12-07 Sgs Microelettrica Spa Densita'.!circuito integrato a semiconduttore, in particolare del tipo comprendente dispositivi ad alta tensione e dispositivi di elaborazione di segnale ad alta
US5173760A (en) * 1987-11-03 1992-12-22 Samsung Electronics Co., Ltd. BiCMOS semiconductor device
JP2906491B2 (ja) * 1989-11-13 1999-06-21 セイコーエプソン株式会社 半導体装置の製造方法
US5262344A (en) * 1990-04-27 1993-11-16 Digital Equipment Corporation N-channel clamp for ESD protection in self-aligned silicided CMOS process
US5283449A (en) * 1990-08-09 1994-02-01 Nec Corporation Semiconductor integrated circuit device including two types of MOSFETS having source/drain region different in sheet resistance from each other
US5246872A (en) * 1991-01-30 1993-09-21 National Semiconductor Corporation Electrostatic discharge protection device and a method for simultaneously forming MOS devices with both lightly doped and non lightly doped source and drain regions
KR100214036B1 (ko) * 1991-02-19 1999-08-02 이데이 노부유끼 알루미늄계 배선형성방법
JP2509412B2 (ja) * 1991-05-09 1996-06-19 サムスン エレクトロニクス カンパニー リミテッド 半導体装置の製造方法
JPH04342164A (ja) * 1991-05-20 1992-11-27 Hitachi Ltd 半導体集積回路装置の形成方法
JPH06268084A (ja) * 1993-03-16 1994-09-22 Seiko Instr Inc 半導体装置の製造方法
JPH07297400A (ja) * 1994-03-01 1995-11-10 Hitachi Ltd 半導体集積回路装置の製造方法およびそれにより得られた半導体集積回路装置
US5529941A (en) * 1994-03-28 1996-06-25 Vlsi Technology, Inc. Method for making an integrated circuit structure
US5516717A (en) * 1995-04-19 1996-05-14 United Microelectronics Corporation Method for manufacturing electrostatic discharge devices
US5532178A (en) * 1995-04-27 1996-07-02 Taiwan Semiconductor Manufacturing Company Gate process for NMOS ESD protection circuits

Also Published As

Publication number Publication date
EP0734067A3 (de) 1998-10-21
JPH08279565A (ja) 1996-10-22
EP0734067A2 (de) 1996-09-25
US5620920A (en) 1997-04-15
DE19510777C1 (de) 1996-06-05

Similar Documents

Publication Publication Date Title
KR960036039A (ko) Esd 보호 기능을 갖는 cmos 구조의 제조 방법
US6277683B1 (en) Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer
KR940001259A (ko) 반도체장치의 제조방법
KR920018977A (ko) 반도체 디바이스 및 집적회로와 그 제조 방법
KR950030278A (ko) 절연게이트 전계 효과 트랜지스터의 제조방법
JP2003124475A (ja) ダブルバーティカルチャネル薄膜トランジスタのｃｍｏｓ装置及びその製造方法
KR960009075A (ko) 박막트랜지스터 및 그 제조방법
KR960042923A (ko) 폴리사이드 구조를 갖는 반도체장치 및 그의 제조방법
US6238984B1 (en) Integrating high voltage and low voltage device with silicide block mask
GB2152283A (en) Gate protection arrangement for a semiconductor device
EP1020922A3 (en) Insulated gate field effect transistor and method of manufacture thereof
KR940012505A (ko) 집적 회로 제조 방법
JPH01181468A (ja) 半導体装置
KR960009064A (ko) Soi mosfet 제조방법
JP3149543B2 (ja) 薄膜トランジスタ
KR0167232B1 (ko) 반도체 매몰 접촉창 형성방법
JPH05235337A (ja) Ｍｉｓ型半導体装置
KR970030927A (ko) 박막 트랜지스터의 제조 방법
KR970053906A (ko) 씨모스(cmos)에서 듀얼 게이트 전극 제조방법
KR970013103A (ko) 모스(MOS) 트랜지스터의 샐리사이드(Salicide) 형성방법
KR980006473A (ko) 반도체 소자의 제조 방법
KR980005883A (ko) 반도체 디바이스의 제조방법
KR920007221A (ko) 스태틱램의 제조방법
KR940022899A (ko) 박막 트랜지스터 제조방법
KR950009927A (ko) 반도체 소자의 실리사이드 제조방법

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid