KR960035909A - 모스 전계효과 트랜지스터의 제조방법 - Google Patents

모스 전계효과 트랜지스터의 제조방법 Download PDF

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KR960035909A
KR960035909A KR1019950004720A KR19950004720A KR960035909A KR 960035909 A KR960035909 A KR 960035909A KR 1019950004720 A KR1019950004720 A KR 1019950004720A KR 19950004720 A KR19950004720 A KR 19950004720A KR 960035909 A KR960035909 A KR 960035909A
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South Korea
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KR1019950004720A
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KR100323445B1 (ko
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정영배
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김주용
현대전자산업 주식회사
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Publication of KR100323445B1 publication Critical patent/KR100323445B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 모스 전계효과 트랜지스터의 제조방법에 관한 것으로서, 열전하 효과를 방지하기 위해, 반도체 기판상에 일련의 게이트전극을 형성한 후, 상기 게이트전극 양측의 반도체기판에 저농도로 불순물을 주입하고, 게이트 전극의 양측에 산화막으로된 스페이서를 형성하며, 상기 스페이서에 의해 노출되어 있는 게이트전극 양측의 반도체기판에 고농도로 불순물을 이주입하여 LDD 구조의 소오스/드레인전극을 형성함에 있어서, LDD구조를 형성하기 위해 사용되는 게이트 전극 측벽에 형성되는 산화막 스페이서의 크기를 식각공정을 통해 그 크기를 줄임으로써 이후 진행되는 공정, 특히 소오스/드레인 전극과 연결되는 콘택홀 형성시 충분한 공간확보를 할 수 있게 함으로써 소자의 공정 단순화 및 효율화를 기할 수 있는 이점이 있다.

Description

모스 전계효과 트랜지스터의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1C도는 본 발명에 따른 모스 전계효과 트랜지스터의 제조공정도.

Claims (4)

  1. 반도체기판에 게이트 산화막을 형성하는 공정과, 상기 게이트 산화막상에 다결정실리콘층 패턴으로된 일련의 게이트전극을 형성하는 공정과, 상기 게이트전극 양측의 반도체기판에 저농도로 불순물을 주입하는 공정과, 게이트 전극의 양측에 산화막으로된 스페이서를 형성하는 공정과, 상기 스페이서에 의해 노출되어 있는 게이트전극 양측의 반도체기판에 고농도로 불순물을 이입주입하는 공정과, 상기 스페이서 산화막의 일부를 식각하여 스페이서의 면적을 줄이는 공정과, 전체 상부에 층간 산화막을 증착한 후 식각하여 상기 소오스/드레인 전극과 연결되는 콘택홀을 형성하는 공정을 구비하는 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.
  2. 제1항에 있어서, 상기 소오스/드레인 전극과 연결되는 콘택홀은 전하저장전극 콘택홀 또는 비트라인 형성 콘택홀인 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.
  3. 제1항에 있어서, 상기 게이트산화막을 70~150Å 두께로 형성하는 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.
  4. 제1항에 있어서, 상기 스페이서 산화막은 최초 면적의 1/2로 축소되도록 식각되는 것을 특징으로 하는 모스 전계효과 트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950004720A 1995-03-08 1995-03-08 모스전계효과트랜지스터의제조방법 KR100323445B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950004720A KR100323445B1 (ko) 1995-03-08 1995-03-08 모스전계효과트랜지스터의제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950004720A KR100323445B1 (ko) 1995-03-08 1995-03-08 모스전계효과트랜지스터의제조방법

Publications (2)

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KR960035909A true KR960035909A (ko) 1996-10-28
KR100323445B1 KR100323445B1 (ko) 2002-05-13

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KR1019950004720A KR100323445B1 (ko) 1995-03-08 1995-03-08 모스전계효과트랜지스터의제조방법

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