KR960026290A - 플라즈마 건식식각 방법 - Google Patents
플라즈마 건식식각 방법 Download PDFInfo
- Publication number
- KR960026290A KR960026290A KR1019940033608A KR19940033608A KR960026290A KR 960026290 A KR960026290 A KR 960026290A KR 1019940033608 A KR1019940033608 A KR 1019940033608A KR 19940033608 A KR19940033608 A KR 19940033608A KR 960026290 A KR960026290 A KR 960026290A
- Authority
- KR
- South Korea
- Prior art keywords
- etched
- mask pattern
- dry etching
- plasma
- etching method
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 5
- 238000001312 dry etching Methods 0.000 title claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명에 의한 플라즈마 건식식각 방법에서는 피식각물질 전면에 피식각물질의 식각부위와 가장자리부위의 표면을 노출시키는 마스크패턴을 형성시키고, 마스크패턴으로 노출시킨 피식각물질의 표면을 플라즈마를 이용하여 식각시켜서, 플라즈마 가스의 집중현상에 의한 과도식각을 감소시킨다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 의한 플라즈마 건식식각 방법에 의해 식각된 웨이퍼 단면을 도식한 도면.
Claims (2)
- 플라즈마를 이용하는 플라즈마 건식식각방법에 있어서, 1) 피식각물질 전면에 식각부위와 가장자리부위의 피식각물질 표면을 노출시키는 소정물질의 미스크패턴을 형성시키는 단계와, 2) 상기 마스크패턴으로 노출시킨 피식각물질의 표면을 플라즈마 가스를 이용하여 식각시키는 단계를 포함하여 이루어진 플라즈마 건식식각 방법.
- 제1항에 있어서, 상기 1)단계에서 피식각물질 전면에 포토레지스트를 도포하여 형성시키고, 식각부위와 가장자리부위의 피식각물질 표면을 노출시키는 마스크패턴을 형성시키는 것을 특징으로 하는 플라즈마 건식식각 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940033608A KR0171070B1 (ko) | 1994-12-10 | 1994-12-10 | 플라즈마 건식식각 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940033608A KR0171070B1 (ko) | 1994-12-10 | 1994-12-10 | 플라즈마 건식식각 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR960026290A true KR960026290A (ko) | 1996-07-22 |
KR0171070B1 KR0171070B1 (ko) | 1999-03-30 |
Family
ID=19400958
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940033608A KR0171070B1 (ko) | 1994-12-10 | 1994-12-10 | 플라즈마 건식식각 방법 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR0171070B1 (ko) |
-
1994
- 1994-12-10 KR KR1019940033608A patent/KR0171070B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR0171070B1 (ko) | 1999-03-30 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR960026290A (ko) | 플라즈마 건식식각 방법 | |
KR970008372A (ko) | 반도체장치의 미세 패턴 형성방법 | |
KR910001875A (ko) | 노광용 마스크의 제조방법 | |
KR910020802A (ko) | 마스크의 제작방법 | |
KR910020833A (ko) | 옥사이드 마스크에 의한 드라이 에칭 방법 | |
KR910005101A (ko) | 레지스트패턴 형성방법 | |
KR970018028A (ko) | 반도체 장치의 금속 콘택 형성방법 | |
KR970023714A (ko) | 반도체 소자의 콘택부 및 그의 형성방법 | |
KR960026351A (ko) | 스페이서절연층 형성방법 | |
KR970076077A (ko) | 더미패턴을 사용하는 반도체소자의 제조방법 | |
KR910001460A (ko) | 포토레지스트의 측벽 프로파일 개선 방법 | |
KR970018192A (ko) | 어노우드(Anode) 전극을 갖는 반도체 식각장치 | |
KR950004390A (ko) | 반도체 소자의 패턴 형성 방법 | |
KR940015687A (ko) | 실리레이션 공정으로 포지티브형 패턴 형성방법 | |
KR970016832A (ko) | 산화막의 습식 에칭방법 | |
KR960002479A (ko) | 반도체 소자의 감광 패턴 형성방법 | |
KR920020591A (ko) | 반도체 장치의 위상시프트 마스크 제조방법 | |
KR980003860A (ko) | 포토레지스트 패턴 형성방법 | |
KR920010808A (ko) | 반도체 제조공정 | |
KR950021045A (ko) | 반도체 소자의 미세 패턴 형성방법 | |
KR920007250A (ko) | 위상반전영역을 갖는 마스크 및 그의 제조방법 | |
KR970062808A (ko) | 위상 반전 마스크의 제조방법 | |
KR900000989A (ko) | 반도체 콘텍트 제조방법 | |
KR970052224A (ko) | 반도체 장치의 접촉장 형성방법 | |
KR940004747A (ko) | 레지스트 패턴형성방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
AMND | Amendment | ||
E601 | Decision to refuse application | ||
J201 | Request for trial against refusal decision | ||
B701 | Decision to grant | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20120924 Year of fee payment: 15 |
|
FPAY | Annual fee payment |
Payment date: 20130916 Year of fee payment: 16 |
|
EXPY | Expiration of term |