KR960012530A - 플래쉬 이이피롬 셀 형성방법 - Google Patents

플래쉬 이이피롬 셀 형성방법 Download PDF

Info

Publication number
KR960012530A
KR960012530A KR1019940024257A KR19940024257A KR960012530A KR 960012530 A KR960012530 A KR 960012530A KR 1019940024257 A KR1019940024257 A KR 1019940024257A KR 19940024257 A KR19940024257 A KR 19940024257A KR 960012530 A KR960012530 A KR 960012530A
Authority
KR
South Korea
Prior art keywords
forming
layer
oxide film
bit line
cell
Prior art date
Application number
KR1019940024257A
Other languages
English (en)
Other versions
KR0150050B1 (ko
Inventor
김명섭
Original Assignee
김주용
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업 주식회사 filed Critical 김주용
Priority to KR1019940024257A priority Critical patent/KR0150050B1/ko
Priority to GB9519088A priority patent/GB2293688B/en
Priority to DE19534921A priority patent/DE19534921C2/de
Priority to US08/534,170 priority patent/US5527727A/en
Publication of KR960012530A publication Critical patent/KR960012530A/ko
Application granted granted Critical
Publication of KR0150050B1 publication Critical patent/KR0150050B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 플래쉬 이이피롬 셀(Flash EEPROM Cell) 형성방법에 관한 것으로, 셀의 소오스 비트라이과 드레인 비트라인(Source ＆ Drain Bit Line) 영역을 BN+층(Buried N+Layer)으로 형성하고, 이후 산화공정으로 BN+층상에 성장되는 BN+산화막은 자기정렬(Self -align) 식각때 약 절반가량이 식각되어 주변부와 토폴러지(Topology) 차이가 거의 없게되고, 후공정의 실렉트 게이트 산화막(Select Gate Oxide) 형성을 위한 산화공정시 BN+산화막은 거의 성장되지 않아 셀의 소오스 드레인 비트라인 영역의 토폴러지가 완화되어 셀 특성을 향상시킬 수 있는 플래수 이이피롬 셀 형성방법에 관한 것이다.

Description

플래쉬 이이피롬 셀 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3A 및 3B도는 본 발명에 의한 플래뤼 이이피롬 셀의 레이아웃도.

Claims (3)

  1. 플래쉬 이이피롬 셀 형성방법에 있어서, 실리콘 기판상 터널 산화막, 플로팅 게이트용 폴리실리콘층, 하부산화막 및 질화막을 순차적으로 적층한 후 활성영역중 소오스 및 드레인 비트라인 영역이 노출되도록 상기 다수 적층된 층을 식각하는 단계와, 상기 단계로부터 불순물 이온주입공정으로 BN+층을 형성하여 소오스 및 드레인 비트라인을 형성하고, 상부 산화막을 형성하여 층간 절연막을 형성하는 단계와, 상기 단계로부터 전체 구조 상부에 컨트롤 게이트용 폴리실리콘층을 형성한 후 마스크 및 자기정렬 식각공정으로 플로팅 게이트와 컨츠롤 게이트롤 형성하는 단계와, 상기 단계로부터 실렉트 게이트 산화막 및 실렉트 게이트를 형성하는 단계로 이루어지는 것을 특징으로 하는 플래쉬 이이피롬 셀 형성방법.
  2. 제1항에 있어서, 상기 층간절연막은 하부 산화막, 질화막, 상부산화막으로 된 ONO 구조인 것을 특징으로 하는 플래쉬 이이피롬 셀 형성방법.
  3. 제1항에 있어서, 상기 상부 산화막은 산화공정에 의해 형성되며, 산화공정시 소오스 및 드레인 비트라인을 이루는 BN+층상에 BN+산화막이 두껍게 성장되고, 두껍게 성장된 BN+산화막은 상기 자기정렬 식각공정시 소정깊이 식각되는 것을 특징으로 하는 플래쉬 이이피 셀 형성방법.
    참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940024257A 1994-09-27 1994-09-27 플래쉬 이이피롬 셀 형성방법 KR0150050B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019940024257A KR0150050B1 (ko) 1994-09-27 1994-09-27 플래쉬 이이피롬 셀 형성방법
GB9519088A GB2293688B (en) 1994-09-27 1995-09-19 Method of manufacturing flash eeprom cells
DE19534921A DE19534921C2 (de) 1994-09-27 1995-09-21 Verfahren zur Herstellung von EEPROM Flash-Zellen mit vergrabenen Bitleitungen
US08/534,170 US5527727A (en) 1994-09-27 1995-09-26 Method of manufacturing split gate EEPROM cells

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940024257A KR0150050B1 (ko) 1994-09-27 1994-09-27 플래쉬 이이피롬 셀 형성방법

Publications (2)

Publication Number Publication Date
KR960012530A true KR960012530A (ko) 1996-04-20
KR0150050B1 KR0150050B1 (ko) 1998-10-01

Family

ID=19393521

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940024257A KR0150050B1 (ko) 1994-09-27 1994-09-27 플래쉬 이이피롬 셀 형성방법

Country Status (4)

Country Link
US (1) US5527727A (ko)
KR (1) KR0150050B1 (ko)
DE (1) DE19534921C2 (ko)
GB (1) GB2293688B (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0851493B9 (en) * 1996-12-27 2007-09-12 STMicroelectronics S.r.l. Contact structure and corresponding manufacturing method for EPROM or flash EPROM semiconductor electronic devices
US6004829A (en) * 1997-09-12 1999-12-21 Taiwan Semiconductor Manufacturing Company Method of increasing end point detection capability of reactive ion etching by adding pad area
US6017795A (en) * 1998-05-06 2000-01-25 Taiwan Semiconductor Manufacturing Company Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash
US6011289A (en) * 1998-09-16 2000-01-04 Advanced Micro Devices, Inc. Metal oxide stack for flash memory application
CN1324690C (zh) * 2001-06-28 2007-07-04 旺宏电子股份有限公司 氮化硅只读存储器的制造方法
US6624025B2 (en) 2001-08-27 2003-09-23 Taiwan Semiconductor Manufacturing Company Method with trench source to increase the coupling of source to floating gate in split gate flash
KR100577011B1 (ko) * 2002-07-10 2006-05-10 매그나칩 반도체 유한회사 반도체소자의 제조방법
JP4481557B2 (ja) * 2002-07-17 2010-06-16 Ｏｋｉセミコンダクタ株式会社 不揮発性半導体記憶装置の製造方法
US20060243524A1 (en) * 2005-04-29 2006-11-02 Raymond Jarrell Collapsible hanging scaffold bracket
CN109461735B (zh) * 2018-10-18 2021-03-26 上海华力微电子有限公司 改善分栅结构闪存多步多晶硅刻蚀损伤的工艺集成方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4795719A (en) * 1984-05-15 1989-01-03 Waferscale Integration, Inc. Self-aligned split gate eprom process
US4852062A (en) * 1987-09-28 1989-07-25 Motorola, Inc. EPROM device using asymmetrical transistor characteristics
US4924437A (en) * 1987-12-09 1990-05-08 Texas Instruments Incorporated Erasable programmable memory including buried diffusion source/drain lines and erase lines
US5162247A (en) * 1988-02-05 1992-11-10 Emanuel Hazani Process for trench-isolated self-aligned split-gate EEPROM transistor and memory array
US5364806A (en) * 1991-08-29 1994-11-15 Hyundai Electronics Industries Co., Ltd. Method of making a self-aligned dual-bit split gate (DSG) flash EEPROM cell
US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
US5313421A (en) * 1992-01-14 1994-05-17 Sundisk Corporation EEPROM with split gate source side injection
US5395779A (en) * 1994-04-08 1995-03-07 United Microelectronics Corporation Process of manufacture of split gate EPROM device

Also Published As

Publication number Publication date
GB2293688B (en) 1998-07-22
KR0150050B1 (ko) 1998-10-01
DE19534921C2 (de) 2002-10-31
US5527727A (en) 1996-06-18
GB2293688A (en) 1996-04-03
GB9519088D0 (en) 1995-11-22
DE19534921A1 (de) 1996-03-28

Similar Documents

Publication Publication Date Title
KR100745003B1 (ko) 반도체 집적 회로 장치 및 그 제조 방법
US5492850A (en) Method for fabricating a stacked capacitor cell in semiconductor memory device
US8325516B2 (en) Semiconductor device with split gate memory cell and fabrication method thereof
US7488634B2 (en) Method for fabricating flash memory device
JPH0563154A (ja) ピン構造の積層型コンデンサを有するｄｒａｍセルの製造方法
KR960036092A (ko) 불휘발성 메모리 제조방법
KR960012530A (ko) 플래쉬 이이피롬 셀 형성방법
KR100231962B1 (ko) 비트라인 사이의 리치스루우 및 비트라인의 인터럽션에 대한 면역성을 제공하는 고밀도로 적층된 분할 게이트 eprom 셀
JP3394859B2 (ja) 半導体記憶装置の製造方法
ATE228719T1 (de) Verbesserte isolierung zwischen diffusions- leitungen in einem speicherfeld
KR970063754A (ko) 플래쉬 이이피롬 셀 제조 방법
KR960036086A (ko) 플래쉬 이이피롬 셀의 제조방법
US7948022B2 (en) Flash memory device and method for manufacturing the same
US6768159B2 (en) Semiconductor device using a polysilicon layer
KR970054236A (ko) 플래쉬 메모리 소자 및 그 제조방법
KR20000076914A (ko) 불휘발성 반도체 기억 장치 및 그 제조 방법
KR950011030B1 (ko) 반도체 장치의 이이피롬 제조방법
KR960039406A (ko) 플래쉬 이이피롬 셀의 제조방법
KR940009645B1 (ko) 불휘발성 메모리장치의 제조방법
KR970013338A (ko) 불휘발성 메모리 장치 및 그 제조 방법
KR930000716B1 (ko) 디램 셀 제조방법
KR100250753B1 (ko) 플래쉬 메모리 셀의 제조 방법
KR970054214A (ko) 플래쉬 메모리 셀의 제조 방법
KR100281139B1 (ko) 비휘발성 메모리소자 및 그의 제조방법
KR100231731B1 (ko) 반도체 소자의 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120524

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee