KR960005874A - 반도체소자의 금속배선 제조방법 - Google Patents

반도체소자의 금속배선 제조방법 Download PDF

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Publication number
KR960005874A
KR960005874A KR1019940017300A KR19940017300A KR960005874A KR 960005874 A KR960005874 A KR 960005874A KR 1019940017300 A KR1019940017300 A KR 1019940017300A KR 19940017300 A KR19940017300 A KR 19940017300A KR 960005874 A KR960005874 A KR 960005874A
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South Korea
Prior art keywords
metal layer
layer
etching
metal wiring
semiconductor device
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KR1019940017300A
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English (en)
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KR100323444B1 (en
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하재희
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김주용
현대전자산업 주식회사
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Priority to KR1019940017300A priority Critical patent/KR100323444B1/ko
Publication of KR960005874A publication Critical patent/KR960005874A/ko
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Publication of KR100323444B1 publication Critical patent/KR100323444B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 금속배선 제조방법에 관한 것으로서, 금속층인 텅스텐층을 불소 플라즈마로 식각하고, 생성되는 폴리머성 잔류물층을 BOE 용액으로 제거한 후, 세척 및 건조시키고 후속공정을 진행하였으므로, 폴리머성 잔류물층에 의한 금속배선 패턴의 임계크기의 증가나 배선패턴의 브릿지 현상을 방지하여 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있다.

Description

반도체 소자의 금속배선 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 및 제1D도는 본 발명에 따른 반도체소자의 금속배선 제조 공정도이다.

Claims (8)

  1. 절연막상에 금속층을 형성하는 공정과, 상기 금속층의 패턴으로 예정되어 있는 부분이 남도록 불소 플라즈마로 패턴닝하여 금속배선을 형성하는 공정과, 상기 구조상에 남아있는 폴리머성 잔류물층을 BOE 용액으로 제거하고 세척하는 공정을 구비하는 반도체소자의 금속배선 제조방법.
  2. 제1항에 있어서, 상기 금속층이 텅스텐층인 것을 특징으로 하는 반도체소자의 금속배선 제조 방법.
  3. 제1항에 있어서, 상기 식각공정이 자기유도 반응성 이온식각, 평판플라즈마식각, 반응성 이온식각 및 이.씨. 알(elecron cyclotron resonace) 식각등으로 이루어지는 군에서 임의로 선택되는 하나의 방법으로 실시하는 것을 특징으로 하는 반도체소자의 금속배선 제조 방법.
  4. 제1항에 있어서, 상기 식각공정을 자기유도 반응성이온식각방법으로하여10±5℃ 정도의 기판온도에서 파워를 400±50W, SF6/Ar에 HBr이나 N2혼합가스 압력을 100±50m Torr 로하여 식각하는 것을 특징으로 하는 반도체 소자의 금속배선 제조방법.
  5. 제1항에 있어서, 상기 절연막과 텅스텐층 사이의 계면 특성 향상을 위하여 베리어 메탈층을 개재시키는 것을 특징으로 하는 반도체소자의 금속배선 제조방법.
  6. 제5항에 있어서, 상기 베리어 메탈층을 Ti이나 Ti/TiN 막으로 형성하는 것을 특징으로하는 반도체 소자의 금속배선 제조방법.
  7. 제6항에 있어서, 상기 베리어 메탈층에 개재되어 있는 경우 상기BOE에 의한 폴리머성 잔류물 제거 공정후, 노출되는 베리어 메탈층을 염소 플라즈마 식각 방법으로 제거하는 것을 특징으로 하는 반도체소자의 금속배선 제조 방법.
  8. 제1항에 있어서, 상기 폴리머성 잔류물 제거 공정을 순수로 7:1 희석된 BOE 용액으로 20-30℃ 의 온도에서 실시하는 것을 특징으로 하는 반도체소자의 금속배선 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940017300A 1994-07-18 1994-07-18 Method for fabricating metal interconnection of semiconductor device KR100323444B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940017300A KR100323444B1 (en) 1994-07-18 1994-07-18 Method for fabricating metal interconnection of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940017300A KR100323444B1 (en) 1994-07-18 1994-07-18 Method for fabricating metal interconnection of semiconductor device

Publications (2)

Publication Number Publication Date
KR960005874A true KR960005874A (ko) 1996-02-23
KR100323444B1 KR100323444B1 (en) 2002-05-13

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KR1019940017300A KR100323444B1 (en) 1994-07-18 1994-07-18 Method for fabricating metal interconnection of semiconductor device

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100471395B1 (ko) * 2001-04-03 2005-03-08 비오이 하이디스 테크놀로지 주식회사 박막 트랜지스터 액정표시장치 제조방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950006976B1 (ko) * 1992-06-03 1995-06-26 현대전자산업주식회사 접촉창 표면세정방법
JPH06125010A (ja) * 1992-10-12 1994-05-06 Fujitsu Ltd 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100471395B1 (ko) * 2001-04-03 2005-03-08 비오이 하이디스 테크놀로지 주식회사 박막 트랜지스터 액정표시장치 제조방법

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