KR100621813B1 - 반도체 소자의 듀얼 다마신 패턴 형성방법 - Google Patents
반도체 소자의 듀얼 다마신 패턴 형성방법 Download PDFInfo
- Publication number
- KR100621813B1 KR100621813B1 KR1020050077449A KR20050077449A KR100621813B1 KR 100621813 B1 KR100621813 B1 KR 100621813B1 KR 1020050077449 A KR1020050077449 A KR 1020050077449A KR 20050077449 A KR20050077449 A KR 20050077449A KR 100621813 B1 KR100621813 B1 KR 100621813B1
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- KR
- South Korea
- Prior art keywords
- via hole
- dual damascene
- interlayer insulating
- diffusion barrier
- semiconductor device
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (8)
- 하부 금속배선이 형성된 반도체 기판을 제공하는 단계;상기 반도체 기판 상에 확산방지막 및 층간절연막을 차례로 형성하는 단계;비아홀 식각 마스크를 이용한 식각 공정을 통해 상기 층간절연막을 패터닝하여, 상기 하부 금속배선과 대응되는 상기 확산방지막의 일부분을 노출시키는 비아홀을 형성하는 단계;상기 노출된 확산방지막의 표면이 산화되도록 결과물에 산화 처리를 수행하는 단계; 및트렌치 식각 마스크를 이용한 식각 공정을 통해 상기 층간절연막의 상부를 패터닝하여, 상기 비아홀을 중심으로 상기 비아홀보다 넓은 트렌치를 형성하는 단계;를 포함하는 반도체 소자의 듀얼 다마신 패턴 형성방법.
- 제 1 항에 있어서,상기 산화 처리는 산소 플라즈마를 이용하여 수행하는 것을 특징으로 하는 반도체 소자의 듀얼 다마신 패턴 형성방법.
- 제 1 항에 있어서,상기 산화 처리는 20℃ 이상의 온도에서 수행하는 것을 특징으로 하는 반도체 소자의 듀얼 다마신 패턴 형성방법.
- 제 1 항에 있어서,상기 층간절연막의 유전상수값은 1 내지 8 인 것을 특징으로 하는 반도체 소자의 듀얼 다마신 패턴 형성방법.
- 제 1 항에 있어서,상기 층간절연막은 PE-TEOS, USG 및 FSG로 구성된 군으로부터 선택되는 어느 하나를 이용하여 형성하는 것을 특징으로 하는 반도체 소자의 듀얼 다마신 패턴 형성방법.
- 제 1 항에 있어서,상기 층간절연막 상에 캡핍층 및 하부 반사방지막을 차례로 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 듀얼 다마신 패턴 형성방법.
- 제 6 항에 있어서,상기 하부 반사방지막은 유기물 또는 무기물로 형성하는 것을 특징으로 하는 반도체 소자의 듀얼 다마신 패턴 형성방법.
- 제 6 항에 있어서,상기 하부 반사방지막은 200 내지 3,000 Å의 두께로 형성하는 것을 특징으 로 하는 반도체 소자의 듀얼 다마신 패턴 형성방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020050077449A KR100621813B1 (ko) | 2005-08-23 | 2005-08-23 | 반도체 소자의 듀얼 다마신 패턴 형성방법 |
Applications Claiming Priority (1)
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KR1020050077449A KR100621813B1 (ko) | 2005-08-23 | 2005-08-23 | 반도체 소자의 듀얼 다마신 패턴 형성방법 |
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KR100621813B1 true KR100621813B1 (ko) | 2006-09-11 |
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KR1020050077449A KR100621813B1 (ko) | 2005-08-23 | 2005-08-23 | 반도체 소자의 듀얼 다마신 패턴 형성방법 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101132887B1 (ko) * | 2005-10-07 | 2012-04-03 | 매그나칩 반도체 유한회사 | 반도체 소자의 듀얼 다마신 패턴 형성방법 |
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2005
- 2005-08-23 KR KR1020050077449A patent/KR100621813B1/ko active IP Right Grant
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101132887B1 (ko) * | 2005-10-07 | 2012-04-03 | 매그나칩 반도체 유한회사 | 반도체 소자의 듀얼 다마신 패턴 형성방법 |
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