KR960002665A - 반도체 소자의 도전층 제조방법 - Google Patents

반도체 소자의 도전층 제조방법 Download PDF

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Publication number
KR960002665A
KR960002665A KR1019940012274A KR19940012274A KR960002665A KR 960002665 A KR960002665 A KR 960002665A KR 1019940012274 A KR1019940012274 A KR 1019940012274A KR 19940012274 A KR19940012274 A KR 19940012274A KR 960002665 A KR960002665 A KR 960002665A
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South Korea
Prior art keywords
conductive layer
teos film
semiconductor device
manufacturing
conductive material
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KR1019940012274A
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KR970006933B1 (ko
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정종호
정종문
정기철
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김주용
현대전자산업 주식회사
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Publication of KR970006933B1 publication Critical patent/KR970006933B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 도전층 제조방법에 관한 것으로, 반사율(feflectance index)이 높은 도전물(예를 들어, 텅스텐 실리사이드, 알루미늄 등)을 이용하여 소자에서 요구되는 도전층을 형성하기 위해 패턴닝(patterning)할 때 도전층의 단면형상(profile)을 양호하게 하기 위하여, 반사율이 높은 도전물상에 반사율이 낮고 제거가 용이한 TEOS막을 얇게 증착한 후 패턴닝 공정을 실시하므로 단면형상이 양호한 도전층을 얻을 수 있는 반도체 소자의 도전층 제조방법에 관한 것이다.

Description

반도체 소자의 도전층 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1A도 내지 제1F도는 본 발명에 의한 반도체 소자의 도전층을 제조하는 방법을 설명하기 위해 도시한 소자의 단면도

Claims (5)

  1. 소자에서 요구되는 단면형상을 얻기 위한 반도체 소자의 도전층 제조방법에 있어서, 소정의 공정을 거친 기판(1)상에 소자에서 요구되는 도전층을 형성하기 위한 소정의 도전물을 증착한 후 그 상부에 TEOS막(4)을 소정두께로 형성하는 단계와, 상기 단계로부터 TEOS막(4)상에 마스크 작업을 통하여 주변회로영역과 셀영역에 패턴화된 제1 및 2포트레지스트(5A, 5B)를 각각 형성하는 단계와, 상기 단계로부터 제1 및 2포토레지스트(5A, 5B)를 식각 장벽층으로 하여 노출부위의 TEOS막(4)을 식각하는 단계와, 상기 단계로부터 제1 및 2포토레지스트(5A, 5B)와 제1 및 2포토레지스트(5A, 5B)의 하부에 담아있는 TEOS막(4)을 식각장벽층으로 하여 노출부위의 도전물을 식각하는 단계와, 상기 단계로부터 제1 및 2포토레지스트(5A, 5B)를 제거한 후, HF 또는 BOE 습식식각용액에 담그어 중합체 및 담아있는 TEOS막(4)을 제거하여 반도체 소자에서 요구되는 단면형상을 갖는 도전층(10)을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 도전층 제조방법
  2. 제1항에 있어서, 상기 도전물은 알루미늄 합금 또는 폴리실리콘위에 텅스텐 실리사이드가 증착된 폴리사이드인 것을 특징으로 하는 반도체 소자의 도전층 제조방법
  3. 제1항에 있어서, 상기 TEOS막(4)은 500∼800Å 정도의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 도전층 제조방법
  4. 제1항에 있어서, 상기 TEOS막(4) 식각시 CF4플라즈마로 식각하는 것을 특징으로 하는 반도체 소자의 도전층 제조방법
  5. 제1항에 있어서, 상기 도전물이 폴리사이드인 경우 텅스텐 실리사이드의 식각제인 SF6와 Cℓ2개스를 사용하여 상기 TEOS막(4) 및 하부의 텅스텐 실리사이드를 순차적으로 식각하는 것을 특징으로 하는 반도체 소자의 도전층 제조방법
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940012274A 1994-06-01 1994-06-01 반도체 소자의 도전층 제조방법 KR970006933B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940012274A KR970006933B1 (ko) 1994-06-01 1994-06-01 반도체 소자의 도전층 제조방법

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Application Number Priority Date Filing Date Title
KR1019940012274A KR970006933B1 (ko) 1994-06-01 1994-06-01 반도체 소자의 도전층 제조방법

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KR960002665A true KR960002665A (ko) 1996-01-26
KR970006933B1 KR970006933B1 (ko) 1997-04-30

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100471395B1 (ko) * 2001-04-03 2005-03-08 비오이 하이디스 테크놀로지 주식회사 박막 트랜지스터 액정표시장치 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100471395B1 (ko) * 2001-04-03 2005-03-08 비오이 하이디스 테크놀로지 주식회사 박막 트랜지스터 액정표시장치 제조방법

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