KR950034711A - 패드 격자 배열 패키지와 플라스틱 적층판 및 그 제조 방법 - Google Patents

패드 격자 배열 패키지와 플라스틱 적층판 및 그 제조 방법 Download PDF

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Publication number
KR950034711A
KR950034711A KR1019950000383A KR19950000383A KR950034711A KR 950034711 A KR950034711 A KR 950034711A KR 1019950000383 A KR1019950000383 A KR 1019950000383A KR 19950000383 A KR19950000383 A KR 19950000383A KR 950034711 A KR950034711 A KR 950034711A
Authority
KR
South Korea
Prior art keywords
substrate
sheet
cavity
pattern
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1019950000383A
Other languages
English (en)
Korean (ko)
Inventor
애디스 박스터 조지
콘 챨스
조셉 새틀러 테오도레
에스. 삭제나 래크쉬멘드라
Original Assignee
오. 이. 알버
에이티앤드티 코포에이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 오. 이. 알버, 에이티앤드티 코포에이션 filed Critical 오. 이. 알버
Publication of KR950034711A publication Critical patent/KR950034711A/ko
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42Fillings
    • H10W76/47Solid or gel fillings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/682Shapes or dispositions thereof comprising holes having chips therein
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/685Shapes or dispositions thereof comprising multiple insulating layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
KR1019950000383A 1994-01-12 1995-01-11 패드 격자 배열 패키지와 플라스틱 적층판 및 그 제조 방법 Ceased KR950034711A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US18024894A 1994-01-12 1994-01-12
US8/180,248 1994-01-12

Publications (1)

Publication Number Publication Date
KR950034711A true KR950034711A (ko) 1995-12-28

Family

ID=22659765

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950000383A Ceased KR950034711A (ko) 1994-01-12 1995-01-11 패드 격자 배열 패키지와 플라스틱 적층판 및 그 제조 방법

Country Status (7)

Country Link
US (1) US5926696A (https=)
EP (1) EP0664562A1 (https=)
JP (1) JP2981141B2 (https=)
KR (1) KR950034711A (https=)
CA (1) CA2134257C (https=)
SG (1) SG52230A1 (https=)
TW (1) TW272311B (https=)

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US6465743B1 (en) * 1994-12-05 2002-10-15 Motorola, Inc. Multi-strand substrate for ball-grid array assemblies and method
GB2301937A (en) * 1995-06-06 1996-12-18 Circuit Components Inc IC package with a ball grid array on a single layer ceramic substrate
KR100386061B1 (ko) * 1995-10-24 2003-08-21 오끼 덴끼 고오교 가부시끼가이샤 크랙을방지하기위한개량된구조를가지는반도체장치및리이드프레임
US5859475A (en) * 1996-04-24 1999-01-12 Amkor Technology, Inc. Carrier strip and molded flex circuit ball grid array
US5852870A (en) 1996-04-24 1998-12-29 Amkor Technology, Inc. Method of making grid array assembly
US5956601A (en) * 1996-04-25 1999-09-21 Kabushiki Kaisha Toshiba Method of mounting a plurality of semiconductor devices in corresponding supporters
US5776798A (en) * 1996-09-04 1998-07-07 Motorola, Inc. Semiconductor package and method thereof
KR100214544B1 (ko) * 1996-12-28 1999-08-02 구본준 볼 그리드 어레이 반도체 패키지
EP0860876A3 (de) * 1997-02-21 1999-09-22 DaimlerChrysler AG Anordnung und Verfahren zur Herstellung von CSP-Gehäusen für elektrische Bauteile
US6172413B1 (en) 1997-10-09 2001-01-09 Micron Technology, Inc. Chip leads constrained in dielectric media
US5919329A (en) * 1997-10-14 1999-07-06 Gore Enterprise Holdings, Inc. Method for assembling an integrated circuit chip package having at least one semiconductor device
US6380001B1 (en) * 1998-01-29 2002-04-30 Vlsi Technology, Inc. Flexible pin count package for semiconductor device
US6232666B1 (en) * 1998-12-04 2001-05-15 Mciron Technology, Inc. Interconnect for packaging semiconductor dice and fabricating BGA packages
US6034425A (en) * 1999-03-17 2000-03-07 Chipmos Technologies Inc. Flat multiple-chip module micro ball grid array packaging
US6288905B1 (en) * 1999-04-15 2001-09-11 Amerasia International Technology Inc. Contact module, as for a smart card, and method for making same
WO2000070677A1 (en) * 1999-05-14 2000-11-23 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device
US6580159B1 (en) * 1999-11-05 2003-06-17 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
JP2001210755A (ja) * 2000-01-28 2001-08-03 Nec Corp 半導体装置用基板および半導体装置の製造方法
DE10014380A1 (de) 2000-03-23 2001-10-04 Infineon Technologies Ag Vorrichtung zum Verpacken von elektronischen Bauteilen
KR20030021405A (ko) * 2001-09-06 2003-03-15 엘지이노텍 주식회사 에어 캐비티를 가지는 플라스틱 패키지
US7224856B2 (en) 2001-10-23 2007-05-29 Digital Optics Corporation Wafer based optical chassis and associated methods
US7961989B2 (en) * 2001-10-23 2011-06-14 Tessera North America, Inc. Optical chassis, camera having an optical chassis, and associated methods
EP1611468B1 (en) * 2003-03-26 2008-05-21 Digital Optics Corporation Package for optoelectronic device on wafer level
US6940724B2 (en) * 2003-04-24 2005-09-06 Power-One Limited DC-DC converter implemented in a land grid array package
US7575955B2 (en) * 2004-01-06 2009-08-18 Ismat Corporation Method for making electronic packages
CN100377327C (zh) * 2004-01-09 2008-03-26 威宇科技测试封装有限公司 对球栅阵列封装的集成电路的重新植球方法
US6888360B1 (en) * 2004-02-20 2005-05-03 Research In Motion Limited Surface mount technology evaluation board having varied board pad characteristics
US7172926B2 (en) * 2004-04-21 2007-02-06 Advanced Semiconductor Engineering, Inc. Method for manufacturing an adhesive substrate with a die-cavity sidewall
AU2005261423B2 (en) * 2004-07-08 2011-03-03 Costruzioni Strumenti Oftalmici C.S.O. S.R.L. Reflection microscope for examination of the corneal endothelium and method of operating same
US7344915B2 (en) * 2005-03-14 2008-03-18 Advanced Semiconductor Engineering, Inc. Method for manufacturing a semiconductor package with a laminated chip cavity
US20070164428A1 (en) * 2006-01-18 2007-07-19 Alan Elbanhawy High power module with open frame package
KR100677184B1 (ko) * 2006-02-10 2007-02-02 삼성전기주식회사 캐비티가 형성된 기판 제조 방법
MY153017A (en) * 2007-02-16 2014-12-31 Sumitomo Bakelite Co Circuit board manufacturing method, semiconductor manufacturing apparatus, circuit board and semiconductor device
KR20090061996A (ko) * 2007-12-12 2009-06-17 삼성전자주식회사 칩 뒷면 보호 필름, 그 제조 방법 및 이를 이용한 반도체패키지의 제조 방법
KR100982795B1 (ko) * 2008-07-10 2010-09-16 삼성전기주식회사 전자소자 내장형 인쇄회로기판 제조방법
EP2461275A1 (en) * 2010-12-02 2012-06-06 Gemalto SA Security Document and method of manufacturing security document
US9299630B2 (en) * 2012-07-30 2016-03-29 General Electric Company Diffusion barrier for surface mount modules
US10269688B2 (en) 2013-03-14 2019-04-23 General Electric Company Power overlay structure and method of making same

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JPS51130866A (en) * 1975-05-08 1976-11-13 Seiko Instr & Electronics Method of mounting electronic timekeeper circuits
US4143456A (en) * 1976-06-28 1979-03-13 Citizen Watch Commpany Ltd. Semiconductor device insulation method
FR2439478A1 (fr) * 1978-10-19 1980-05-16 Cii Honeywell Bull Boitier plat pour dispositifs a circuits integres
DE3248385A1 (de) * 1982-12-28 1984-06-28 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Ausweiskarte mit integriertem schaltkreis
JPS59138339A (ja) * 1983-01-28 1984-08-08 Toshiba Corp 半導体装置
US4819041A (en) * 1983-12-30 1989-04-04 Amp Incorporated Surface mounted integrated circuit chip package and method for making same
US4916522A (en) * 1988-04-21 1990-04-10 American Telephone And Telegraph Company , At & T Bell Laboratories Integrated circuit package using plastic encapsulant
US5258647A (en) * 1989-07-03 1993-11-02 General Electric Company Electronic systems disposed in a high force environment
FR2651923B1 (fr) * 1989-09-14 1994-06-17 Peugeot Circuit integre de puissance.
JPH03211757A (ja) * 1989-12-21 1991-09-17 General Electric Co <Ge> 気密封じの物体
US5241133A (en) * 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
US5557142A (en) * 1991-02-04 1996-09-17 Motorola, Inc. Shielded semiconductor device package
US5102829A (en) * 1991-07-22 1992-04-07 At&T Bell Laboratories Plastic pin grid array package
JPH05109922A (ja) * 1991-10-21 1993-04-30 Nec Corp 半導体装置
US5285352A (en) * 1992-07-15 1994-02-08 Motorola, Inc. Pad array semiconductor device with thermal conductor and process for making the same
US5371404A (en) * 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
US5420460A (en) * 1993-08-05 1995-05-30 Vlsi Technology, Inc. Thin cavity down ball grid array package based on wirebond technology
US5455456A (en) * 1993-09-15 1995-10-03 Lsi Logic Corporation Integrated circuit package lid

Also Published As

Publication number Publication date
CA2134257A1 (en) 1995-07-13
JP2981141B2 (ja) 1999-11-22
TW272311B (https=) 1996-03-11
JPH07212002A (ja) 1995-08-11
CA2134257C (en) 1998-12-15
US5926696A (en) 1999-07-20
EP0664562A1 (en) 1995-07-26
SG52230A1 (en) 1998-09-28

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