KR950033860A - 데이타 프로세서 및 이것을 사용한 트레이스회로 - Google Patents

데이타 프로세서 및 이것을 사용한 트레이스회로 Download PDF

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Publication number
KR950033860A
KR950033860A KR1019950002035A KR19950002035A KR950033860A KR 950033860 A KR950033860 A KR 950033860A KR 1019950002035 A KR1019950002035 A KR 1019950002035A KR 19950002035 A KR19950002035 A KR 19950002035A KR 950033860 A KR950033860 A KR 950033860A
Authority
KR
South Korea
Prior art keywords
signal
bus
cache
data processor
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019950002035A
Other languages
English (en)
Korean (ko)
Inventor
슈우야 후지따
요시까즈 아오또
아쯔시 하세가와
히데아끼 고야마
노보루 스기하라
슌뻬이 가와사끼
Original Assignee
가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
오야 유이찌로
가부시끼가이샤 하다찌마이컴시스템
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가나이 쯔또무, 가부시끼가이샤 히다찌세이사꾸쇼, 오야 유이찌로, 가부시끼가이샤 하다찌마이컴시스템 filed Critical 가나이 쯔또무
Publication of KR950033860A publication Critical patent/KR950033860A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Prevention of errors by analysis, debugging or testing of software
    • G06F11/362—Debugging of software
    • G06F11/3636—Debugging of software by tracing the execution of the program

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
KR1019950002035A 1994-02-09 1995-02-06 데이타 프로세서 및 이것을 사용한 트레이스회로 Withdrawn KR950033860A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP94-36496 1994-02-09
JP3649694 1994-02-09
JP6259727A JPH07271705A (ja) 1994-02-09 1994-09-30 データプロセッサ及びこれを用いたトレース回路
JP94-259727 1994-09-30

Publications (1)

Publication Number Publication Date
KR950033860A true KR950033860A (ko) 1995-12-26

Family

ID=26375556

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950002035A Withdrawn KR950033860A (ko) 1994-02-09 1995-02-06 데이타 프로세서 및 이것을 사용한 트레이스회로

Country Status (4)

Country Link
EP (1) EP0667576A1 (enExample)
JP (1) JPH07271705A (enExample)
KR (1) KR950033860A (enExample)
TW (1) TW305960B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3934710B2 (ja) * 1996-09-13 2007-06-20 株式会社ルネサステクノロジ マイクロプロセッサ
JP3214613B2 (ja) 1998-07-03 2001-10-02 日本電気株式会社 マイクロプロセッサ及びデータ処理システム
GB2362968B (en) 1999-12-23 2003-12-10 St Microelectronics Sa Computer system with debug facility
GB2362730B (en) 1999-12-23 2004-02-11 St Microelectronics Sa Computer register watch
GB2365546B (en) 1999-12-23 2004-02-18 St Microelectronics Sa A computer system with two debug watch modes
GB2362729B (en) 1999-12-23 2004-02-11 St Microelectronics Sa Memory access debug facility
GB2366006B (en) 1999-12-23 2004-06-30 St Microelectronics Sa A computer system with debug facility
ATE535868T1 (de) * 2007-04-18 2011-12-15 Mediatek Inc Verfahren und vorrichtung zur aufzeichnung von datenadressen

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0371418A3 (en) * 1988-11-30 1991-09-04 National Semiconductor Corporation Apparatus for and method of providing the program counter of a microprocessor external to the device
DE69127992T2 (de) * 1990-04-20 1998-06-04 Hitachi Ltd Mikroprozessor zur Buszykluseinfügung zwecks Informationslieferung für eine Emulation

Also Published As

Publication number Publication date
TW305960B (enExample) 1997-05-21
EP0667576A1 (en) 1995-08-16
JPH07271705A (ja) 1995-10-20

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19950206

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid