TW305960B - - Google Patents

Download PDF

Info

Publication number
TW305960B
TW305960B TW084100845A TW84100845A TW305960B TW 305960 B TW305960 B TW 305960B TW 084100845 A TW084100845 A TW 084100845A TW 84100845 A TW84100845 A TW 84100845A TW 305960 B TW305960 B TW 305960B
Authority
TW
Taiwan
Prior art keywords
signal
external
bus
cache
access
Prior art date
Application number
TW084100845A
Other languages
English (en)
Chinese (zh)
Original Assignee
Hitachi Ltd
Hitachi Microcomp System Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomp System Kk filed Critical Hitachi Ltd
Application granted granted Critical
Publication of TW305960B publication Critical patent/TW305960B/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/36Prevention of errors by analysis, debugging or testing of software
    • G06F11/362Debugging of software
    • G06F11/3636Debugging of software by tracing the execution of the program

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
TW084100845A 1994-02-09 1995-01-28 TW305960B (enExample)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3649694 1994-02-09
JP6259727A JPH07271705A (ja) 1994-02-09 1994-09-30 データプロセッサ及びこれを用いたトレース回路

Publications (1)

Publication Number Publication Date
TW305960B true TW305960B (enExample) 1997-05-21

Family

ID=26375556

Family Applications (1)

Application Number Title Priority Date Filing Date
TW084100845A TW305960B (enExample) 1994-02-09 1995-01-28

Country Status (4)

Country Link
EP (1) EP0667576A1 (enExample)
JP (1) JPH07271705A (enExample)
KR (1) KR950033860A (enExample)
TW (1) TW305960B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3934710B2 (ja) * 1996-09-13 2007-06-20 株式会社ルネサステクノロジ マイクロプロセッサ
JP3214613B2 (ja) 1998-07-03 2001-10-02 日本電気株式会社 マイクロプロセッサ及びデータ処理システム
GB2362729B (en) 1999-12-23 2004-02-11 St Microelectronics Sa Memory access debug facility
GB2362968B (en) 1999-12-23 2003-12-10 St Microelectronics Sa Computer system with debug facility
GB2362730B (en) 1999-12-23 2004-02-11 St Microelectronics Sa Computer register watch
GB2366006B (en) 1999-12-23 2004-06-30 St Microelectronics Sa A computer system with debug facility
GB2365546B (en) 1999-12-23 2004-02-18 St Microelectronics Sa A computer system with two debug watch modes
ATE535868T1 (de) * 2007-04-18 2011-12-15 Mediatek Inc Verfahren und vorrichtung zur aufzeichnung von datenadressen

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0371418A3 (en) * 1988-11-30 1991-09-04 National Semiconductor Corporation Apparatus for and method of providing the program counter of a microprocessor external to the device
EP0453268B1 (en) * 1990-04-20 1997-10-22 Hitachi, Ltd. A microprocessor for inserting a bus cycle to output an internal information for an emulation

Also Published As

Publication number Publication date
EP0667576A1 (en) 1995-08-16
KR950033860A (ko) 1995-12-26
JPH07271705A (ja) 1995-10-20

Similar Documents

Publication Publication Date Title
TW552515B (en) Input/output (I/O) address translation in a bridge proximate to a local I/O bus
Roth Axiomatic models of bargaining
EP0422103B1 (en) I/o bus to system bus interface
TWI254211B (en) System-on-a-chip
TW384440B (en) A method and apparatus for data ordering of I/O transfers in bi-modal endian power PC systems
TW200842592A (en) Improved DMAc to handle transfers of unknown lengths
TW200915087A (en) Bridge device with page-access based processor interface
TW305960B (enExample)
TW201140094A (en) Test apparatus and test method
TWI336478B (en) Semiconductor memory apparatus and data masking method of the same
TWM298188U (en) Control device for accessing Non-Volatile memory
JPS582922A (ja) 装置とコンピユ−タの間でデ−タを交換するためのバツフアおよび方法
JPS6187451A (ja) ディジタルデータ通信システム
TW201131578A (en) Memory management method, memory controller and memory storage system
JPS61138330A (ja) バツフア回路
JPH04139565A (ja) マルチcpu装置
JPH0773132A (ja) 内部メモリマップレジスタを観察する方法及び装置
TWI294078B (en) Device and method for accessing memory
JPS60502073A (ja) ワンチツプ・マイクロプロセツサを結合する回路装置
TWI250416B (en) Interference and system for transporting real-time data
CN100468382C (zh) 四倍频地址总线的系统与方法
TWI225591B (en) Apparatus and method for computer bus cycle single-step interrupt debugging via personal computer memory card interface association (PCMCIA) interface
JP2609685B2 (ja) リセット回路
JPH03167648A (ja) ダイレクトメモリアクセス制御装置
JPS598057A (ja) メモリ装置