KR950015830A - 트랜지스터 및 수직형 트랜지스터 - Google Patents

트랜지스터 및 수직형 트랜지스터 Download PDF

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KR950015830A
KR950015830A KR1019940030710A KR19940030710A KR950015830A KR 950015830 A KR950015830 A KR 950015830A KR 1019940030710 A KR1019940030710 A KR 1019940030710A KR 19940030710 A KR19940030710 A KR 19940030710A KR 950015830 A KR950015830 A KR 950015830A
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피. 로브 스티븐
엘. 프레게일 윌리엄
제이. 그론니그 파울
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빈센트 비. 인그라시아
모토로라 인코포레이티드
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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Abstract

트랜지스터(200)는 단일 공통베이스 영역(202)을 포함한다. 하나이상의 소스영역(112)은 베이스 영역(202)에 형성된다. 하나이상의 게이트 영역(120)은 공통베이스(202) 및 소스영역(112)위에 놓인다. 다른 실시예에 있어서, 게이트 영역(320)은 분기된 중심부(321)를 갖는다. 또다른 실시예에 있어서, 소정의 소스영역(402)은 교차 접속된다. 따라서, 폴리실리콘 패턴(602)은 게이트 핑거 피트 네트워크(614, 616, 618)와, 가장 긴 다이 크기의 1/2 이하의 길이를 갖는 게이트 핑거(604, 606, 608, 620)를 제공하는데 사용된다.

Description

트랜지스터 및 수직형 트랜지스터
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일실시예에 따른 수직형 MOS 트랜지스터의 개략적인 횡단면도,
제2도는 본 발명의 일실시예에 따른 트랜지스터의 개략적인 평면도.
제3도는 본 발명에 따른 트랜지스터의 다른 실시예의 계략적인 횡단면도.
제4도는 본 발명에 따른 트랜지스터의 다른 실시예의 부분 평면도.

Claims (5)

  1. 트랜지스터가 제1 표면(118) 및 상기 제1 표면(118)에 평행한 제2 표면(122)과, 상기 제1 표면(118)에서 상기 제2표면(122)으로 전류를 전도하기 위해 구성된 트랜지스터를 구비하는 수직으로 적층된 반도체 구조(100)와, 단일 공통 베이스 영역(202) 및, 제1 재료를 구비하고, 단일 공통 베이스 영역(202)에 형성된 하나이상의 소스 영역을 포함하는데, 상기 하나 이상의 소스영역(112)중 소정 인접한 한 영역은 제1 재료와 교차 접속되는 것을 특징으로 하는 트랜지스터.
  2. 트랜지스터가 공통 베이스 영역(202)과, 상기 공통 베이스 영역(202)에 형성된 하나 이상의 소스영역(112) 및, 상기 공통 베이스 영역(202)과하나 이상의 소스영역(112)을 겹치는 하나 이상의 게이트 영역(120)을 포함하는데, 각각의 게이트 영역(120)이 횡단면을 갖는 연장된 게이트 핑거(32O)와 중심부(321)와 상기 엣지부(322)를 갖는 횡단면을 포함하고, 상기 중심부(321)는 엣지부(322)보다 더 두꺼운 것을 특징으로 하는 트랜지스터.
  3. 수직형 트랜지스터가 공통 스트라이프형 베이스 영역(202)과, 제1 도핑된 재료와, 공통 스트라이프형 베이스 영역(202)에 형성된 다수의 소스영역(510)과, 상기 제1 도핑된 재료와 교차 접속(512)되어지는 소스 영역중 소정인접 영역 및, 공통 스트라이프형 베이스영역(22) 및 하나 이상의 소스영역(510)을 겹치는 하나 이상의 게이트 핑거(120)를 포함하는 수직형 트랜지스터.
  4. 트랜지스터가 길이와 폭을 가진 반도체 다이(600)와, 다수의 게이트 핑거(604, 606, 608, 610)와 다수의 소스 접촉 영역(112)을 노출시키는 패턴 형성된 게이트 영역(602)과, 게이트 피드 네트워크(614, 616, 618)와, 게이트 핑거상의 가장 먼 지점으로부터 게이트 피드 네트워크(614, 616, 618)까지의 거리인 게이트 핑거 길이를 가진 다수의 각 게이트 핑거(604, 606, 608, 610)와 다수의 소스 접촉영역(112)으로부터 전기적으로 절연되는 게이트 피드(614, 616, 618)네트워크와 연속해서 전기적으로 결합되는 다수의 소스접촉 영역(112)과 접촉하는 단일금속 레벨(700))을 포함하는데, 최대 게이트 핑거길이는 비교적 큰 반도체 다이길이 및 폭의 1/2 이하인 것을 특징으로 하는 트랜지스터.
  5. 트랜지스터가 정열된 게이트 핑거(604, 606, 608, 610)이를 다수의 병혈로 분산시킨 다수의 소스영역(112)과 연속해서 전기적으로 결합되는 다수의 소스영역(112)과, 다수의 게이트 핑거(604, 606, 608, 610) 모두에 전기적 접촉을 제공하는 단일금속 레벨(700) 및, 단일 금속 레벨의 일부(704)를 통해 다수의 소스영역(112)에 접촉하는 단일외부 전기적 접촉부(710)를 포함하는 것을 특징으로 하는 트랜지스터.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940030710A 1993-11-22 1994-11-22 트랜지스터 및 수직형 트랜지스터 KR950015830A (ko)

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US15550493A 1993-11-22 1993-11-22
US155,504 1993-11-22
US272,899 1994-07-08
US08/272,899 US5396097A (en) 1993-11-22 1994-07-08 Transistor with common base region

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US (1) US5396097A (ko)
EP (2) EP0655787A3 (ko)
JP (1) JPH07193243A (ko)
KR (1) KR950015830A (ko)
CN (1) CN1034841C (ko)
SG (1) SG43005A1 (ko)

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Publication number Publication date
EP0655787A3 (en) 1995-08-16
SG43005A1 (en) 1997-10-17
CN1034841C (zh) 1997-05-07
EP0655787A2 (en) 1995-05-31
JPH07193243A (ja) 1995-07-28
US5396097A (en) 1995-03-07
CN1108814A (zh) 1995-09-20
EP0827209A1 (en) 1998-03-04

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