KR950012770A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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KR950012770A
KR950012770A KR1019940027399A KR19940027399A KR950012770A KR 950012770 A KR950012770 A KR 950012770A KR 1019940027399 A KR1019940027399 A KR 1019940027399A KR 19940027399 A KR19940027399 A KR 19940027399A KR 950012770 A KR950012770 A KR 950012770A
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semiconductor layer
insulating film
forming
gate
electrode
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KR0178824B1 (ko
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요시로 바바
사토시 야나기야
노보루 마츠다
아키히코 오사와
마사노부 츠치타니
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사토 후미오
가부시키가이샤 도시바
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0843—Source or drain regions of field-effect devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

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Abstract

[목적] 신뢰성이 높고, 특성면에서 안정한 항시 온형의 종형 파워 MOS FET를 갖춘 반도체장치 및 그것을 저가, 고수율로 제조할 수 있는 제조방법을 제공한다.
[구성] 기판표면에 대해 2중확산에 의해 채널영역(12) 및 소오스영역(13)을 형성하고, 이 채널영역 및 소오스 영역의 일부를 관통하여 기판에 도달하도록 트렌치(14)를 형성하며, 이 트렌치의 내벽에 절연막(15)을 형성한후, 트렌치 중간부까지 이온주입 마스크재(16)를 매립한 상태에서 트렌치 측면영역에 채널 이온주입 행해 채널부를 디플리션화하고, 이 후 트렌치에 게이트인출전극(18)을 매립하는 것을 특징으로 한다.

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 N채널 종형 파워 MOS FET의 평면패턴의 일례를 나타낸 도면,
제2도는 제1도중의 B-B선에 따른 단면도,
제3도는 본 발명의 제1실시예에 따른 N채널 종형 파워 MOS FET의 형성방법에 따른 각 공정에서의 기판단면을 나타낸 도면이다.

Claims (2)

  1. 제1도전형의 반도체기판(10)과, 이 반도체기판(10)의 주면에 설치된 저불순물농도를 갖는 드레인영역용의 제1도전형의 제1반도체층(11), 이 제1반도체층(11)의 상면에 설치된 채널영역 형성용의 제2전도형의 제2반도체층(12), 이 제2반도체층(12)의 표층부의 일부에 설치된 소오스영역용의 제1도전형이 제3반도체층(13), 이 제3반도체층(13)의 표면으로부터 상기 제2반도체층(12)의 일부를 관통하여 상기 제1반도체층(11)에 도달하도록 설치된 단면이 거의 U자 모양인 도량(14)의 내측면에 형성된 게이트절연막용의 제1절연막(15), 이 게이트절연막(15)상에서 상기 도량(14)의 중간부까지 매립된 이온주입 마스크재(16), 이 이온주입 마스크재(16)상에 형성된 제2절연막(17), 이 제2절연막(17)상에서 상기 도량(14)을 매립하도록 설치된 게이트인 출전극(18), 이 게이트인 출전극(18)상, 상기 제1반도체층(11)의 표면상, 상기 제2반도체층(12)의 표면상 및 상기 제3반도체층(13)의 표면상을 피복하도록 설치된 제3절연막(19), 이 제3절연막(19)에 설치된 접촉구멍을 매개로 상기 게이트인출전극(18)에 접촉하는 게이트전극(G), 상기 제3절연막(19)에 설치된 접촉구멍을 매개로 상기 제2반도체층(12)의 표면 및 제3반도체층(13)의 표면에 공통으로 접촉하는 소오스 전극(S) 및, 상기 반도체기판(10)의 이면에 설치된 드레인 전극(D)을 구비한 것을 특징으로 하는 반도체장치.
  2. 제1도전형의 반도체기판의 주면에 저불순물농도를 갖는 드레인영역용의 제1도전형의 제1반도체층을 형성하는 공정과, 2중확산법에 의해 상기 제1반도체층의 상면에 채널영역 형성용의 제2도전형의 제2반도체층을 형성하고, 이 제2반도체층의 표층부의 일부에 소오스영역용의 제1도전형의 제3반도체층을 형성하는 공정, 이 제3반도체층의 표면으로부터 상기 제2반도체층의 일부를 관통하여 상기 제1반도체층에 도달하도록 단면이 거의 U자모양인 도량을 형성하는 공정, 이 도량의 내측면에 게이트절연막용의 제1절연막을 형성하는 공정, 이 게이트절연막상에서 상기 도랑의 중간부까지 이온주입 마스크재를 매립하는 공정, 상기 도랑내에서 노출하고 있는 제1절연막을 제거하는 공정, 경사이온주입법에 의해 상기 도랑이 노출하고 있는 내벽면에 채널이온주입을 행하는 공정, 상기 이온주입 마스크재상에 제2절연막을 형성하는 공정, 이 제2절연막상에서 상기 도랑을 매립하도록 게이트인출전극을 형성하는 공정, 이 게이트인출전극상, 상기 제1반도체층의 표면상, 상기 제2반도체층의 표면상 및 상기 제3반도체층의 표면상을 피복하도록 제3절연막을 형성하는 공정, 이 제3절연막에 접촉 구멍을 개구한 후에 금속막을 퇴적하고 패터닝함으로써, 상기 게이트인출전극에 접촉하는 게이트전극 및 상기 제2반도체층의 표면과 제3반도체층의 표면에 공통으로 접촉하는 소오스전극을 형성하는 공정 및, 상기 반도체기판의 이면에 드레인전극을 형성하는 공정을 구비한 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940027399A 1993-10-28 1994-10-26 반도체장치 및 그 제조방법 KR0178824B1 (ko)

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JP93-270650 1993-10-28
JP27065093A JP3383377B2 (ja) 1993-10-28 1993-10-28 トレンチ構造の縦型のノーマリーオン型のパワーｍｏｓｆｅｔおよびその製造方法

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