KR950010733A - 멀티 칩 모듈 및 그 제조방법 - Google Patents

멀티 칩 모듈 및 그 제조방법 Download PDF

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KR950010733A
KR950010733A KR1019940024927A KR19940024927A KR950010733A KR 950010733 A KR950010733 A KR 950010733A KR 1019940024927 A KR1019940024927 A KR 1019940024927A KR 19940024927 A KR19940024927 A KR 19940024927A KR 950010733 A KR950010733 A KR 950010733A
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multilayer wiring
mounting
ceramic multilayer
wiring board
input
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KR1019940024927A
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요시타카 후쿠다
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사토 후미오
가부시키가이샤 도시바
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Publication of KR950010733A publication Critical patent/KR950010733A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/14—Integrated circuits
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은, 안정한 기능을 항상 유지·발휘하는 것이 가능한 MCM 및 낮은 비용으로 수율 좋고 신뢰성 높은 MCM을 제조하여 얻는 방법의 제공을 목적으로 한다.
본 발명은, 세라믹계 다층배선 기판(1)과 상기 세라믹계 다층배선 기판(1)의 원하는 영역면에서 마운트·본딩된 칩형의 전자부품(2), 상기 전자부품(2)의 실장영역을 둘러싸 세라믹계 다층배선 기판(1)면에 배치된 쉴링층(5), 상기 쉴링층(5)에서 개구단 테두리부(6a)가 밀착되어 실장부품(2)을 밀장하는 밀봉체(6), 상기 밀봉체(6)의 밀착부에서는 세라믹계 다층배선 기판(1)을 내층배선시켜 밀착부의 외주영역에서 세라믹계 다층배선 기판(1)면에서 도출·접속된 입출력단자 핀 취부용 패드(4a)를 구비하여 이루어지고, 상기 입출력단자 부착용 패드(4a)가 열상태로 배치되면서 각 패드(4a)에 대한 내층배선의 도출부가 서로 위치를 엇갈리게 하는 것을 특징으로 한다. 더욱이, MCM의 제조방법은 실장용 세라믹계 다층배선 기판(1)을 형성하고, 상기 형성한 실장용 세라믹계 다층배선 기판(1)면에서 소요의 칩형의전자부품을 마운트·본딩한 후 상기 전자부품을 마운트·본딩한 주변부면의 입출력단자 부착용 패드(4a)에서 융점 400℃이하의 납 재료로 입출력단사 핀을 납땜하는 공정을 구비하여 이루어진 것을 특징으로 한다.

Description

멀티 칩 모듈및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 MCM의 주요부 구성예를 도시한 평면도.
제2도는 본 발명에 따른 MCM의 다른 주요부 구성예를 도시한 평면도.
제3도는 본 발명에 따른 MCM의 제조방법의 공정예를 도시한 플로우챠트도.
제4도는 본 발명에 따른 MCM의 다른 제조방법의 공정예를 도시한 플로우챠트도.
제5도는 본 발명에 따른 MCM의 주요부 구성을 도시한 단면도.
제6도는 본 발명에 따른 MCM의 제조방법의공정을 도시한 플로우챠트도이다.

Claims (4)

  1. 세라믹계 다층배선 기판(1)과 상기 세라믹계 다층배선 기판(1)의 원하는 영역면에 마운트·본딩된 칩형의 전자부품(2), 상기 전자부품(2)의 실장영역을 둘러싸 세라믹계 다층배선 기판(1)면에 배치된 쉴링층(5), 상기 쉴링층(5)에서 개구단 테두리부(6a)가 밀착되어 실장부품을 밀장하는 밀봉체(6), 상기 밀봉체(6)의 밀착부에서는 세라믹계 다층배선 기판내를을 내층배선시켜 밀착부의 외주영역에서 세라믹계 다층배선 기판(1)면에 도출·접속된 입출력단자 부착용 패드(4a)를 구비하고 있고, 상기 입출력단자 부착용 패드(4a)가 열상태로 배치되면서 각 패드에 대한 내층배선의 도출부(4b) 서로 위치를 엇갈리게 하는 것을 특징으로 하는 멀티 칩 모듈.
  2. 제1항에 있어서, 서로 위치가 엇갈리게 하는 내층배선의 도출부(4b)를 피복하여 형성하는 입출력단자 부착용 패드(4a)를 멀티 칩 모듈의 입출력단자 구조로 대응하여 구성하는 것을 특징으로 하는 멀티 칩 모듈.
  3. 실장용 세라믹계 다층배선 기판(1)을 형성하는 제1공정과 상기 형성한 실장용 세라믹계 다층배선 기판(1)에서 소요의 칩형의 전자부품을 마운트·본딩하는 제2공정 및, 상기 전자부품을 마운트·본딩한 주변부면의 입출력단자 부착용 패드에서 융점 400℃이하의 납 재료로 입출력단자를 납땜하는 제3공정을 구비하여 이루어진 것을 특징으로 하는 멀티 칩 모듈의 제조방법.
  4. 실장용 세라믹계 다층배선 기판(1)을 형성하는 제1공정과, 상기 형성한 실장용 세라믹계 다층배선 기판(1)면에서 소요의 칩형의 전자부품을 마운트·본딩하는 제2공정 및, 상기 전자부품을 마운트·본딩한 주변부면의입출력단자 부착용 패드(4a)에서 융점 400℃이하의 납 재료로 입출력단자를 납땜함과 동시에 전자부품의 실제마운트 ·본딩역역을 둘러싸 배치된 쉴링층에서 융점 400℃이하의 납 재료로 밀봉체의 개구단 테두리부를 밀착하는 제3공정을 구비하여 이루어진 것을 특징으로 하는 멀티 칩 모듈의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940024927A 1993-09-30 1994-09-30 멀티 칩 모듈 및 그 제조방법 KR950010733A (ko)

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JP24530493A JP3210503B2 (ja) 1993-09-30 1993-09-30 マルチチップモジュールおよびその製造方法
JP93-245304 1993-09-30

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KR950010733A true KR950010733A (ko) 1995-04-28

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KR100333306B1 (ko) * 1991-09-10 2002-08-14 소니 가부시끼 가이샤 텔레비전세트

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WO1996039716A1 (en) * 1995-06-06 1996-12-12 International Business Machines Corporation Multilayer module with thinfilm redistribution area

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JPH063836B2 (ja) * 1982-03-31 1994-01-12 株式会社東芝 マルチチツプモジュール
JPS5980957A (ja) * 1982-10-29 1984-05-10 Matsushita Electronics Corp 半導体装置
JPS59151443A (ja) * 1983-02-17 1984-08-29 Fujitsu Ltd 半導体装置
JPH0634452B2 (ja) * 1985-08-05 1994-05-02 株式会社日立製作所 セラミツクス回路基板
JPH0714105B2 (ja) * 1986-05-19 1995-02-15 日本電装株式会社 混成集積回路基板及びその製造方法
JP2670505B2 (ja) * 1988-10-03 1997-10-29 イビデン株式会社 電子部品搭載用基板
SE9100597D0 (sv) * 1991-03-01 1991-03-01 Carlstedt Elektronik Ab Kapsel foer vlsi-wafer
EP0547807A3 (en) * 1991-12-16 1993-09-22 General Electric Company Packaged electronic system
JP2960276B2 (ja) * 1992-07-30 1999-10-06 株式会社東芝 多層配線基板、この基板を用いた半導体装置及び多層配線基板の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100333306B1 (ko) * 1991-09-10 2002-08-14 소니 가부시끼 가이샤 텔레비전세트

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