KR970067817A - 반도체 패키지 및 그 제조방법 - Google Patents

반도체 패키지 및 그 제조방법 Download PDF

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KR970067817A
KR970067817A KR1019960006372A KR19960006372A KR970067817A KR 970067817 A KR970067817 A KR 970067817A KR 1019960006372 A KR1019960006372 A KR 1019960006372A KR 19960006372 A KR19960006372 A KR 19960006372A KR 970067817 A KR970067817 A KR 970067817A
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semiconductor
semiconductor package
conductor
semiconductor chip
package according
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KR1019960006372A
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KR100206893B1 (ko
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김진성
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문정환
엘지반도체 주식회사
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Priority to KR1019960006372A priority Critical patent/KR100206893B1/ko
Priority to US08/751,615 priority patent/US5838061A/en
Priority to JP9052612A priority patent/JP2936320B2/ja
Publication of KR970067817A publication Critical patent/KR970067817A/ko
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Publication of KR100206893B1 publication Critical patent/KR100206893B1/ko

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Abstract

본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로, 종래의 일반적인 비지에이(BGA) 패키지는 경박단 소화에 한계가 있고, 500핀 이상의 다핀화가 불가능하며, 시간이 많이 소요되고 고가장비가 필요한 문제점이 있었던 바, 본 발명 반도체 패키지는 서브스트레이트의 상면에 형성된 안착부에 반도체 칩을 설치하고, 종래의 와이어 본딩을 배제함으로써 패키지를 경박단소화 시키는 효과가 있으며, 또한, 내, 외부 단자의 넓이를 0.2×0.2㎟ 정조의 크기로 함으로써 패키지의 다핀화를 가능케 하는 효과가 있을 뿐 아니라, 종래의 와이어 본딩 혹은 범프를 이용한 플립칩 방법을 배제하고 전도체를 매개로 열압착 방법으로 반도체 칩을 실장함으로써 시간 및 공정이 절감되고 고가장비가 불필요하여 생산성 향상 및 원가절감의 효과가 있다.

Description

반도체 패키지 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명 반도체 패키지의 구조를 보인 종단면도.

Claims (12)

  1. 다수개의 내,외부단자가 내부리드로 연결되도록 설치되고 안착부가 형성된 서브스트레이트와, 상기 내부단자의 상면에 각각 설치되는 전도체와, 그 전도체의 상면에 각각 설치되는 반도체 칩과, 그 반도체 칩을 감싸도록 상기 안착부에 몰딩되는 몰딩부를 구비하여서 구성된 것을 특징으로 하는 반도체 패키지.
  2. 제1항에 있어서, 상기 반도체 칩의 상면이 외부로 노출되도록 몰딩부를 형성하여 열방출이 용하도록 한 것을 특징으로 하는 반도체 패키지.
  3. 제1항에 있어서, 상기 안착부에 적어도 2개 이상의 반도체 칩이 실장된 것을 특징으로 하는 반도체 패키지.
  4. 제3항에 있어서, 상기 안착부에 실장된 적어도 2개 이상의 반도체 칩의 상면이 외부로 노출되도록 몰딩된 것을 특징으로 하는 반도체 패키지.
  5. 제1항에 있어서, 상기 내부리드는 동박배선인 것을 특징으로 하는 반도체 패키지.
  6. 제1항에 있어서, 상기 내,외부단자가 Cu이며, 그 Cu에 접합력을 향상시키기 위하여 Au 또는 Ni을 증착한 것을 특징으로 하는 반도체 패키지.
  7. 제1항에 있어서, 상기 서브스트레이트는 피시비 또는 세라믹 기판중의 어느 하나인 것을 특징으로 하는 반도체 패키지.
  8. 제1항에 있어서, 상기 전도체는 ACA 또는 ACF 중 어느 하나인 것을 특징으로 하는 반도체 패키지.
  9. 서브스트레이트에 설치된 다수개의 내부단자 상면에 전도체를 도포하고, 상기 전도체의 상면에 각각 반도체 칩의 칩패드를 얼라인하여 열압착 한 후, 상기 반도체 칩을 감싸도록 몰딩을 하는 순서로 진행되는 것을 특징으로 하는 반도체 패키지 제조방법.
  10. 제9항에 있어서, 상기 서브스트레이트는 피시비 또는 세라믹 기판중 어느 하나인 것을 특징으로 하는 반도체 패키지 제조방법.
  11. 제9항에 있어서, 상기 전도체는 ACA 또는 ACF 중 어느 하나인 것을 특징으로 하는 반도체 패키지 제조방법.
  12. 안착부와 연결부가 형성되고 다수개의 내, 외부단자가 내부리드로 연결되는 적어도 2개 이상의 적층된 서브스트레이트와, 상기 내부단자의 상면에 각각 설치되는 전도체와, 상기 안착부에 위치한 전도체의 상면에 설치되는 각각의 반도체 칩과, 그 각각의 반도체 칩을 감싸도록 형성된 몰딩부를 구비하여서 구성된 것을 특징으로 하는 반도체 패키지.
KR1019960006372A 1996-03-11 1996-03-11 반도체 패키지 및 그 제조방법 KR100206893B1 (ko)

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US08/751,615 US5838061A (en) 1996-03-11 1996-11-18 Semiconductor package including a semiconductor chip adhesively bonded thereto
JP9052612A JP2936320B2 (ja) 1996-03-11 1997-03-07 半導体パッケージ

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