KR950004410A - 반도체장치의 게이트형성방법 - Google Patents

반도체장치의 게이트형성방법 Download PDF

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Publication number
KR950004410A
KR950004410A KR1019930013692A KR930013692A KR950004410A KR 950004410 A KR950004410 A KR 950004410A KR 1019930013692 A KR1019930013692 A KR 1019930013692A KR 930013692 A KR930013692 A KR 930013692A KR 950004410 A KR950004410 A KR 950004410A
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South Korea
Prior art keywords
semiconductor device
gate
polysilicon
deposited
melting point
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KR1019930013692A
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English (en)
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KR0135166B1 (ko
Inventor
변정수
김형준
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문정환
금성일렉트론 주식회사
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Priority to KR1019930013692A priority Critical patent/KR0135166B1/ko
Priority to DE4420052A priority patent/DE4420052C2/de
Priority to JP6189005A priority patent/JP2707415B2/ja
Publication of KR950004410A publication Critical patent/KR950004410A/ko
Priority to US08/565,634 priority patent/US5712181A/en
Application granted granted Critical
Publication of KR0135166B1 publication Critical patent/KR0135166B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체장치의 게이트형성방법에 관한 것으로, 붕소침투 및 폴리사이드의 열적분안정 요인에 의한 불량을 방지하기 위하여 게이트로서 폴리실리콘/비정질실리콘/게이트절연막의 구조를 증착하고 BF2 +를 이온주입한 고융점 금속을 증착하고 실리사이드화 하여 폴리사이드를 형성한다.

Description

반도체장치의 게이트형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도 및 제 2 도는 본 발명의 제 1 실시예를 나타낸 도면, 제 3 도 내지 제 4 도는 본 발명의 제 2 실시예를 나타낸 도면이다.

Claims (5)

  1. 반도체기판상에 형성된 게이트절연막상에 비정질실리콘과 폴리실리콘을 연속적으로 증착한 후, 소정의 불순물을 이온주입하고 열처리하는 공정을 포함함을 특징으로 하는 반도체장치의 게이트형성방법.
  2. 제 1 항에 있어서, 상기 불순물로 BF2 +를 이온주입함을 특징으로 하는 반도체장치의 게이트형성방법.
  3. 제 1 항에 있어서, 상기 공정후에 상기 폴리실리콘층 상에 고융점 금속을 증착하고 열처리하여 폴리사이드를 형성하는 공정이 더 포함됨을 특징으로 하는 반도체장치의 게이트형성방법.
  4. 제 3 항에 있어서, 상기 고융점 금속으로 Co를 증착함을 특징으로 하는 반도체장치의 게이트형성방법.
  5. 제 3 항에 있어서, 상기 폴리실리콘을 폴리사이드 형성시 소모되리라고 예상되는 두께만큼 증착함을 특징으로 하는 반도체장치의 게이트형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930013692A 1993-07-20 1993-07-20 반도체장치의 게이트 형성방법 KR0135166B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019930013692A KR0135166B1 (ko) 1993-07-20 1993-07-20 반도체장치의 게이트 형성방법
DE4420052A DE4420052C2 (de) 1993-07-20 1994-06-08 Verfahren zur Herstellung eines Silizid-Gates für MOS-Halbleitereinrichtungen
JP6189005A JP2707415B2 (ja) 1993-07-20 1994-07-20 半導体装置のゲート形成方法
US08/565,634 US5712181A (en) 1993-07-20 1995-11-29 Method for the formation of polycide gate in semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930013692A KR0135166B1 (ko) 1993-07-20 1993-07-20 반도체장치의 게이트 형성방법

Publications (2)

Publication Number Publication Date
KR950004410A true KR950004410A (ko) 1995-02-18
KR0135166B1 KR0135166B1 (ko) 1998-04-25

Family

ID=19359624

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930013692A KR0135166B1 (ko) 1993-07-20 1993-07-20 반도체장치의 게이트 형성방법

Country Status (4)

Country Link
US (1) US5712181A (ko)
JP (1) JP2707415B2 (ko)
KR (1) KR0135166B1 (ko)
DE (1) DE4420052C2 (ko)

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Publication number Priority date Publication date Assignee Title
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Also Published As

Publication number Publication date
DE4420052C2 (de) 1997-07-17
JPH07147260A (ja) 1995-06-06
US5712181A (en) 1998-01-27
KR0135166B1 (ko) 1998-04-25
JP2707415B2 (ja) 1998-01-28
DE4420052A1 (de) 1995-01-26

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