KR940008772B1 - 전기적 비아 구조물 및 그 형성방법 - Google Patents

전기적 비아 구조물 및 그 형성방법 Download PDF

Info

Publication number
KR940008772B1
KR940008772B1 KR1019910006785A KR910006785A KR940008772B1 KR 940008772 B1 KR940008772 B1 KR 940008772B1 KR 1019910006785 A KR1019910006785 A KR 1019910006785A KR 910006785 A KR910006785 A KR 910006785A KR 940008772 B1 KR940008772 B1 KR 940008772B1
Authority
KR
South Korea
Prior art keywords
layer
mask
dielectric
photoresist
window
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019910006785A
Other languages
English (en)
Korean (ko)
Inventor
에이. 트라스크 필립
지. 베이키트 가브리엘
에이. 필라이 빈센트
알. 오스본 커크
제이. 버그 캐쓰린
비. 워린 개리
Original Assignee
휴우즈 에어크라프트 캄파니
완다 케이. 덴슨-로우
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 휴우즈 에어크라프트 캄파니, 완다 케이. 덴슨-로우 filed Critical 휴우즈 에어크라프트 캄파니
Application granted granted Critical
Publication of KR940008772B1 publication Critical patent/KR940008772B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
KR1019910006785A 1990-04-27 1991-04-26 전기적 비아 구조물 및 그 형성방법 Expired - Lifetime KR940008772B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US515,813 1990-04-27
US07/515,813 US5034091A (en) 1990-04-27 1990-04-27 Method of forming an electrical via structure

Publications (1)

Publication Number Publication Date
KR940008772B1 true KR940008772B1 (ko) 1994-09-26

Family

ID=24052850

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910006785A Expired - Lifetime KR940008772B1 (ko) 1990-04-27 1991-04-26 전기적 비아 구조물 및 그 형성방법

Country Status (5)

Country Link
US (1) US5034091A (enExample)
EP (1) EP0454384A3 (enExample)
JP (1) JPH04229627A (enExample)
KR (1) KR940008772B1 (enExample)
TW (1) TW199234B (enExample)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5531020A (en) * 1989-11-14 1996-07-02 Poly Flex Circuits, Inc. Method of making subsurface electronic circuits
US5180689A (en) * 1991-09-10 1993-01-19 Taiwan Semiconductor Manufacturing Company Tapered opening sidewall with multi-step etching process
JP3161040B2 (ja) * 1992-06-16 2001-04-25 ソニー株式会社 半導体装置の製造方法
US5633122A (en) * 1993-08-16 1997-05-27 Micron Technology, Inc. Test fixture and method for producing a test fixture for testing unpackaged semiconductor die
JP2951215B2 (ja) * 1993-09-10 1999-09-20 レイセオン・カンパニー 位相マスクレーザによる微細なパターンの電子相互接続構造の製造方法
US5474956A (en) * 1995-03-14 1995-12-12 Hughes Aircraft Company Method of fabricating metallized substrates using an organic etch block layer
US5770884A (en) * 1995-06-30 1998-06-23 International Business Machines Corporation Very dense integrated circuit package
US5737152A (en) * 1995-10-27 1998-04-07 Quantum Corporation Suspension with multi-layered integrated conductor trace array for optimized electrical parameters
US5916733A (en) * 1995-12-11 1999-06-29 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor device
JPH09306901A (ja) * 1996-05-17 1997-11-28 Nec Corp 半導体装置の製造方法
US5995328A (en) * 1996-10-03 1999-11-30 Quantum Corporation Multi-layered integrated conductor trace array interconnect structure having optimized electrical parameters
US5814885A (en) * 1997-04-28 1998-09-29 International Business Machines Corporation Very dense integrated circuit package
US6087199A (en) * 1998-02-04 2000-07-11 International Business Machines Corporation Method for fabricating a very dense chip package
US5998868A (en) * 1998-02-04 1999-12-07 International Business Machines Corporation Very dense chip package
US6025638A (en) * 1998-06-01 2000-02-15 International Business Machines Corporation Structure for precision multichip assembly
US6232235B1 (en) * 1998-06-03 2001-05-15 Motorola, Inc. Method of forming a semiconductor device
US6066513A (en) * 1998-10-02 2000-05-23 International Business Machines Corporation Process for precise multichip integration and product thereof
US6274291B1 (en) 1998-11-18 2001-08-14 International Business Machines Corporation Method of reducing defects in I/C card and resulting card
JP2000286549A (ja) 1999-03-24 2000-10-13 Fujitsu Ltd バイアコネクションを備えた基板の製造方法
US6333553B1 (en) 1999-05-21 2001-12-25 International Business Machines Corporation Wafer thickness compensation for interchip planarity
JP3387478B2 (ja) * 1999-06-30 2003-03-17 セイコーエプソン株式会社 半導体装置およびその製造方法
JP3973340B2 (ja) * 1999-10-05 2007-09-12 Ｎｅｃエレクトロニクス株式会社 半導体装置、配線基板、及び、それらの製造方法
JP2001267747A (ja) * 2000-03-22 2001-09-28 Nitto Denko Corp 多層回路基板の製造方法
US6627998B1 (en) * 2000-07-27 2003-09-30 International Business Machines Corporation Wafer scale thin film package
US6734369B1 (en) * 2000-08-31 2004-05-11 International Business Machines Corporation Surface laminar circuit board having pad disposed within a through hole
US6629367B2 (en) 2000-12-06 2003-10-07 Motorola, Inc. Electrically isolated via in a multilayer ceramic package
JP2002251793A (ja) * 2001-02-21 2002-09-06 Sony Corp 光記録媒体原盤の作製方法
JP2002353195A (ja) * 2001-05-23 2002-12-06 Sony Corp 半導体装置の製造方法
GB2387026A (en) * 2002-03-28 2003-10-01 Zarlink Semiconductor Ltd Method of coating contact holes in MEMS and micro-machining applications
JP2004128063A (ja) * 2002-09-30 2004-04-22 Toshiba Corp 半導体装置及びその製造方法
US7276794B2 (en) * 2005-03-02 2007-10-02 Endevco Corporation Junction-isolated vias
US8762917B2 (en) 2012-01-13 2014-06-24 AWR Corporation Automatically modifying a circuit layout to perform electromagnetic simulation
US8813020B2 (en) 2012-01-13 2014-08-19 AWR Corporation Automatically modifying a circuit layout to perform electromagnetic simulation
US8772058B2 (en) * 2012-02-02 2014-07-08 Harris Corporation Method for making a redistributed wafer using transferrable redistribution layers
CN116013853B (zh) * 2023-03-27 2023-06-02 合肥晶合集成电路股份有限公司 互连结构的制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3986912A (en) * 1975-09-04 1976-10-19 International Business Machines Corporation Process for controlling the wall inclination of a plasma etched via hole
JPS5453863A (en) * 1977-10-05 1979-04-27 Sanyo Electric Co Ltd Forming method of insulation films
US4386116A (en) * 1981-12-24 1983-05-31 International Business Machines Corporation Process for making multilayer integrated circuit substrate
DE3215410A1 (de) * 1982-04-24 1983-10-27 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen von oeffnungen mit hilfe einer maske in einer auf einer unterlage befindlichen schicht
US4461672A (en) * 1982-11-18 1984-07-24 Texas Instruments, Inc. Process for etching tapered vias in silicon dioxide
US4426249A (en) * 1983-06-30 1984-01-17 Rca Corporation Composition and thickness variation in dielectric layers
US4484978A (en) * 1983-09-23 1984-11-27 Fairchild Camera & Instrument Corp. Etching method
JPS60136338A (ja) * 1983-12-26 1985-07-19 Hitachi Ltd 半導体装置
US4645562A (en) * 1985-04-29 1987-02-24 Hughes Aircraft Company Double layer photoresist technique for side-wall profile control in plasma etching processes
US4631248A (en) * 1985-06-21 1986-12-23 Lsi Logic Corporation Method for forming an electrical contact in an integrated circuit
IT1200785B (it) * 1985-10-14 1989-01-27 Sgs Microelettronica Spa Migliorato procedimento di attaco in plasma (rie) per realizzare contatti metallo-semiconduttore di tipo ohmico
DE3776325D1 (de) * 1987-04-16 1992-03-05 Ibm Verfahren zur herstellung von kontaktoeffnungen in einer doppellagenisolation.

Also Published As

Publication number Publication date
TW199234B (enExample) 1993-02-01
JPH04229627A (ja) 1992-08-19
EP0454384A3 (en) 1992-03-18
EP0454384A2 (en) 1991-10-30
US5034091A (en) 1991-07-23

Similar Documents

Publication Publication Date Title
KR940008772B1 (ko) 전기적 비아 구조물 및 그 형성방법
KR100268213B1 (ko) 무바닥형라이너구조체의형성방법및반도체제품
US4721689A (en) Method for simultaneously forming an interconnection level and via studs
KR100201035B1 (ko) 자동 정렬 야금술
JPH06505833A (ja) マルチチップモジュールおよび平坦化パターン化表面を有する集積回路基板
EP0370935B1 (en) Method of forming conductive lines and studs
US6048445A (en) Method of forming a metal line utilizing electroplating
JPS61182245A (ja) 複数の半導体集積回路を接続する薄膜状の相互接続信号面を形成する方法及び素子
CA1226680A (en) Process for forming vias on integrated circuits
US5200300A (en) Methods for forming high density multi-chip carriers
KR100293080B1 (ko) 반도체장치제조방법
JP3557166B2 (ja) 半導体素子の接触部形成方法
US20030186536A1 (en) Via formation in integrated circuits by use of sacrificial structures
KR100462764B1 (ko) 이종 감광막을 이용한 듀얼 다마신 방법
KR100460064B1 (ko) 반도체 소자의 금속배선 형성방법
KR20010009036A (ko) 반도체장치의 배선 및 그 연결부 형성방법
US4970573A (en) Self-planarized gold interconnect layer
KR20030049571A (ko) 듀얼-다마신 공정을 이용한 반도체 소자의 금속배선형성방법
KR100368090B1 (ko) 비감광성폴리이미드수지절연막의콘택홀형성방법
KR100440259B1 (ko) 반도체 소자의 듀얼 다마신 패턴 형성 방법
KR100440471B1 (ko) 반도체 소자 제조 방법
KR100232224B1 (ko) 반도체소자의 배선 형성방법
KR100576414B1 (ko) 반도체 소자의 랜딩 비아 제조 방법
KR20000012966A (ko) 반도체 장치의 콘택 제조방법
KR100186515B1 (ko) 반도체 소자의 배선 제작 방법

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

G160 Decision to publish patent application
PG1605 Publication of application before grant of patent

St.27 status event code: A-2-2-Q10-Q13-nap-PG1605

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

NORF Unpaid initial registration fee
PC1904 Unpaid initial registration fee

St.27 status event code: A-2-2-U10-U13-oth-PC1904

St.27 status event code: N-2-6-B10-B12-nap-PC1904

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000