KR940008129A - 박막트랜지스터 및 그 제조방법 - Google Patents

박막트랜지스터 및 그 제조방법 Download PDF

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Publication number
KR940008129A
KR940008129A KR1019920017811A KR920017811A KR940008129A KR 940008129 A KR940008129 A KR 940008129A KR 1019920017811 A KR1019920017811 A KR 1019920017811A KR 920017811 A KR920017811 A KR 920017811A KR 940008129 A KR940008129 A KR 940008129A
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South Korea
Prior art keywords
film
semiconductor layer
gate
drain
insulating film
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KR1019920017811A
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English (en)
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KR950005485B1 (ko
Inventor
소희섭
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이헌조
주식회사 금성사
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Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019920017811A priority Critical patent/KR950005485B1/ko
Priority to US08/127,812 priority patent/US5422287A/en
Priority to JP24284993A priority patent/JP3587867B2/ja
Publication of KR940008129A publication Critical patent/KR940008129A/ko
Application granted granted Critical
Publication of KR950005485B1 publication Critical patent/KR950005485B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본 발명은 박막트랜지스터 및 그의 제조방법에 관한 것으로 종래에는 기판위에 반도체층 및 게이트 절연막을 형성한후 게이트를 형성하고, 상기 반도체층에 이온주입공정으로 불순물을 주입하여 소스·드레인을 형성하여 반도체층과 게이트 절연막 사이의 계면 결함에 의해 누설전류가 발생하여 액정표시소자용 스위치로서 특성이 떨어져 성능을 저하시키는 문제점이 있었다.
본 발명은 상기와 같은 종래의 문제점을 감안하여 산화막보다 유전율이 좋은 질화 실리콘막으로 산화방지막을 형성한 후 반도체 층을 산화시켜 산화막으로 형성하고 상기 반도체층 일부에 이온주입으로 소스·드레인을 형성하여 구동시 누설전류를 감소시키고 반도체층 단차를 감소시켜 단선을 방지하여 소자의 성능개선 및 신뢰성을 향상하는 효과가 있다.

Description

박막트랜지스터 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도의 (가) 내지 (마)는 본 발명의 박막트랜지스터 제조공정을 보인 단면도.
제 3도는 본 발명의 다른 실시예를 보인 단면도.

Claims (6)

  1. 기판 (1)위에 반도체층(2)을 증착한 후 일부를 산화시켜 게이트절연막(3)을 형성한 다음 산화방지막(8)을 증착후 패터닝하는 단계와, 상기 반도체층(2) 일부를 산화시켜 산화막(10)을 형성하는 단계와, 상기 산화방지막(8)위에 게이트(4)를 형성하는 단계와, 그 게이트(4) 일부를 산화시켜 산화막(9)으로 형성하는 단계와, 상기 산화방지막(8) 일부를 식각시킨 후 소스·드레인(5) 형성하는 단계와, 전면에 절연막(11) 형성 후 선택적식각으로 상기 게이트(4)와, 소스·드레인(5) 일부에 접촉 홀을 형성하는 단계와, 그 접촉 홀에 금속을 증착하여 전극(7)을 형성하는 단계로 제조하는 박막트랜지스터 제조방법.
  2. 제1항에 있어서, 산화방지막(8)은 지로하 실리콘막(Si3N4)으로 제조하는 박막트랜지스터 제조방법.
  3. 제1항에 있어서, 게이트 절연막(3), 산화막(9)(10)은 열산화 방법으로 제조하는 박막트랜지스터 제조방법.
  4. 제1항에 있어서, 소스·드레인(5)에 이온주입공정으로 고도핑 반도체층(12) 형성하여 제조하는 박막트랜지스터 제조방법.
  5. 기판(1)상에 반도체층(2)이 삽입된 소스·드레인(5)이 형성되고, 그 반도체층(2)위에 게이트 절연막(3), 산화방지막(8) 및 게이트 (4)가 형성되고, 그 게이트(4)와 상기 소스·드레인(5)위에 접촉 홀을 갖는 산화막(9) 및 절연막(11) 과 산화막(10) 및 절연막(11) 이 각기 형성되며, 상기 게이트(4), 소스·드레인(5)위에 전극(7)이 구비된 구조의 박막트랜지스터.
  6. 제5항에 있어서, 상기 게이트(4) 끝부분과 소스·드레인(5) 끝부분은 격리된 거리(△L)를 갖는 구조의 박막트랜지스터.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920017811A 1992-09-29 1992-09-29 박막트랜지스터 및 그 제조방법 KR950005485B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019920017811A KR950005485B1 (ko) 1992-09-29 1992-09-29 박막트랜지스터 및 그 제조방법
US08/127,812 US5422287A (en) 1992-09-29 1993-09-28 Thin film transistor and process for producing the same
JP24284993A JP3587867B2 (ja) 1992-09-29 1993-09-29 薄膜トランジスタ及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920017811A KR950005485B1 (ko) 1992-09-29 1992-09-29 박막트랜지스터 및 그 제조방법

Publications (2)

Publication Number Publication Date
KR940008129A true KR940008129A (ko) 1994-04-28
KR950005485B1 KR950005485B1 (ko) 1995-05-24

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US (1) US5422287A (ko)
JP (1) JP3587867B2 (ko)
KR (1) KR950005485B1 (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5663077A (en) * 1993-07-27 1997-09-02 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a thin film transistor in which the gate insulator comprises two oxide films
JP3313840B2 (ja) * 1993-09-14 2002-08-12 富士通株式会社 半導体装置の製造方法
US6897100B2 (en) 1993-11-05 2005-05-24 Semiconductor Energy Laboratory Co., Ltd. Method for processing semiconductor device apparatus for processing a semiconductor and apparatus for processing semiconductor device
CN1052566C (zh) * 1993-11-05 2000-05-17 株式会社半导体能源研究所 制造半导体器件的方法
US5780352A (en) * 1995-10-23 1998-07-14 Motorola, Inc. Method of forming an isolation oxide for silicon-on-insulator technology
US5573961A (en) * 1995-11-09 1996-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Method of making a body contact for a MOSFET device fabricated in an SOI layer
JP3717634B2 (ja) * 1997-06-17 2005-11-16 株式会社半導体エネルギー研究所 半導体装置の作製方法
TW408351B (en) * 1997-10-17 2000-10-11 Semiconductor Energy Lab Semiconductor device and method of manufacturing the same
JP4126156B2 (ja) * 1998-01-30 2008-07-30 株式会社日立製作所 液晶表示装置
US6781646B2 (en) 2000-07-28 2004-08-24 Hitachi, Ltd. Liquid crystal display device having gate electrode with two conducting layers, one used for self-aligned formation of the TFT semiconductor regions
JP2004152962A (ja) * 2002-10-30 2004-05-27 Oki Electric Ind Co Ltd 半導体装置の製造方法
US20070252233A1 (en) * 2006-04-28 2007-11-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the semiconductor device

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Publication number Priority date Publication date Assignee Title
US4104087A (en) * 1977-04-07 1978-08-01 The United States Of America As Represented By The Secretary Of The Air Force Method for fabricating MNOS memory circuits
US4192059A (en) * 1978-06-06 1980-03-11 Rockwell International Corporation Process for and structure of high density VLSI circuits, having inherently self-aligned gates and contacts for FET devices and conducting lines
US4466172A (en) * 1979-01-08 1984-08-21 American Microsystems, Inc. Method for fabricating MOS device with self-aligned contacts

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US5422287A (en) 1995-06-06
JP3587867B2 (ja) 2004-11-10
JPH06196703A (ja) 1994-07-15
KR950005485B1 (ko) 1995-05-24

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