KR940006265A - 소거검증 및 어드레스 스크램 블링구조의 플래시 이-이-피-롬(eeprom)과 그 소거방법 - Google Patents

소거검증 및 어드레스 스크램 블링구조의 플래시 이-이-피-롬(eeprom)과 그 소거방법 Download PDF

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Publication number
KR940006265A
KR940006265A KR1019930012872A KR930012872A KR940006265A KR 940006265 A KR940006265 A KR 940006265A KR 1019930012872 A KR1019930012872 A KR 1019930012872A KR 930012872 A KR930012872 A KR 930012872A KR 940006265 A KR940006265 A KR 940006265A
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South Korea
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address
storage area
verification
memory cell
erasing
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KR1019930012872A
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English (en)
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히로미 노부가다
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오가 노리오
소니 가부시기가이샤
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Priority claimed from JP20717392A external-priority patent/JPH0628875A/ja
Priority claimed from JP26301792A external-priority patent/JPH0684386A/ja
Application filed by 오가 노리오, 소니 가부시기가이샤 filed Critical 오가 노리오
Publication of KR940006265A publication Critical patent/KR940006265A/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0615—Address space extension
    • G06F12/0623—Address space extension for memory modules
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

본 발명은 메모리셀의 임계전압의 소정치에 도달할 때까지 소거및 검증동작을 반복하고, 비선택영역에 어떠한 과소거메모리셀이 존재하더라도 검증이 가능하도록 검증시 비선택열의 각 셀의 제어게이트전극에 부(負)전압을 인가하고, 과소거셀이 과서거상태로부터 해제되도록 재기록함으로써, 메모리셀과 임계전압의 분포가 좁은 영역에 설정되는 것이 가능하다. 그리고, 외부지정어드레스를 내부칩어드레스로 변환하기 위한 수단을 구비함으로써, 외부어드레스에 의해 지정된 저장영역이 데이타가 소거될 때마다 칩에서 시프트되거나 순환되므로, 플래시 EEPROM 내에서 반복가능한 재프로그래밍동작의 회수가 현저하게 증가된다.

Description

소거검증 및 어드레스 스크램 블링구조의 플래시 이-이-피-롬(EEPR0M)과 그 소거방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명에서의 소거사이클에 관한 신호의 타이밍차트,
제6도는 본 발명에서의 임계전압 조정사이클에 관한 신호의 타이밍차트,
제7도는 본 발명에서의 메모리셀의 임계전압의 분포를 도식적으로 나타낸 도면.

Claims (7)

  1. 각 메모리셀의 임피던스가 독출 또는 검증시에 상승되도록 소거동작을 하기 전에 소거될 메모리셀의 임계전압의 집합적인 시프트를 행하는 단계, 상기 메모리셀의 임계전압이 제1결정전압에 도달할 때까지 소거 및 검증동작을 반복하는 단계로 이루어지고, 검증시 비선택열의 각 메모리셀의 제어게이트전극에 부전압을 인가하는 것을 특징으로 하는 플래시 EEPROM 소거방법.
  2. 제1항에 있어서, 검증 후의 부가적인 소거동작은 전체 플래시 EEPROM칩 또는 다수의 열을 구성하는 메모리블럭에 집합적으로 행하여지는 것을 특징으로 하는 플래시 EEPROM 소거방법.
  3. 제1항에 있어서, 검증 후의 부가적인 소거동작은 열마다 행하여지는 것을 특징으로 하는 플래시 EEPROM 소거방법.
  4. 각 메모리셀의 임피던스가 독출 또는 검증시에 상승되도록 소거동작을 하기 전에 소거될 메모리셀의 임계전압의 집합적인 시프트를 행하는 단계, 상기 메모리셀의 임계전압이 제1결정전압에 도달할 때까지 소거 검증동작을 반복하는 단계, 제1및 제2결정전압 사이의 임계전압을 유지하도록 소거동작후의 검증시 제1결정전압보다 낮은 제2결정전압에 도달된 메모리셀의 임계전압을 시프트시키는 단계로 이루어지고, 검증시 비선택열의 메모리셀의 제어게이트전극에 부전압을 인가하는 것을 특징으로 하는 플래시 EEPROM 소거방법.
  5. 다수의 블럭으로 구성된 저장영역을 갖추고, 외부지정어드레스를 내부칩어드레스로 변환하기 위한 어드레스컨버터를 구비하고, 다수의 블럭의 상기 저정영역은 상기 외부지정어드레스에 대응하는 상기 내부칩어드레스에 대해 시프트 또는 순환되는 것을 특징으로 하는 플래시 EEPROM 소거방법
  6. 제5항에 있어서, 상기 어드레스컨버터는 최상위비트(MSB)의 어드레스신호를사용하여 어드레스변환을 행하는 것을 특징으로 하는 플래시 EEPROM 소거방법.
  7. 특정저장영역을 위한 적어도 하나의 예비저장영역을 갖추고, 외부지정어드레스를 내부칩 어드레스로 변환하기 위한 어드레스컨버터를 구비하고, 상기 외부지정어드레스에 대응하는 상기 내부칩어드레스에 대한 저장영역은 상기 특정저장영역과 상기 예비 저장영역사이에서 시프트 또는 순환되는 것을 특징으로 하는 플래시 EEPROM 소거 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930012872A 1992-07-10 1993-07-09 소거검증 및 어드레스 스크램 블링구조의 플래시 이-이-피-롬(eeprom)과 그 소거방법 KR940006265A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP20717392A JPH0628875A (ja) 1992-07-10 1992-07-10 フラッシュ型ｅ２ ｐｒｏｍの消去方法
JP92-207,173 1992-07-10
JP92-263,017 1992-09-04
JP26301792A JPH0684386A (ja) 1992-09-04 1992-09-04 フラッシュ型ｅ２ ｐｒｏｍ

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KR940006265A true KR940006265A (ko) 1994-03-23

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US (2) US5909395A (ko)
EP (1) EP0596198B1 (ko)
KR (1) KR940006265A (ko)

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KR100495655B1 (ko) * 1997-11-25 2005-09-20 삼성전자주식회사 반도체메모리장치및그장치의오버소거검증방법
KR100502565B1 (ko) * 1998-10-27 2005-09-30 주식회사 하이닉스반도체 플래쉬 메모리셀의 소거 확인 회로

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