KR940003070A - 반도체소자의 단위소자간 격리방법 - Google Patents

반도체소자의 단위소자간 격리방법 Download PDF

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Publication number
KR940003070A
KR940003070A KR1019920012254A KR920012254A KR940003070A KR 940003070 A KR940003070 A KR 940003070A KR 1019920012254 A KR1019920012254 A KR 1019920012254A KR 920012254 A KR920012254 A KR 920012254A KR 940003070 A KR940003070 A KR 940003070A
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KR
South Korea
Prior art keywords
silicon
film
etching
oxide film
sidewalls
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KR1019920012254A
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English (en)
Inventor
이창재
양희식
Original Assignee
문정환
금성일렉트론 주식회사
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019920012254A priority Critical patent/KR940003070A/ko
Priority to TW082104254A priority patent/TW239903B/zh
Priority to DE4320062A priority patent/DE4320062C2/de
Priority to JP5170138A priority patent/JPH06163532A/ja
Priority to US08/089,868 priority patent/US5374584A/en
Publication of KR940003070A publication Critical patent/KR940003070A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

본발명은 MOS형 실리콘 반도체의 소자제조공정에서 개별소자와 소자의 격리방법에 있어서, (1) 실리콘기관에 일반적인 CMOS 제조방법에 따라 원하는 농도로 도찡된 웰공정을 실시하고, 실리콘기판을 기체 O2및/또는 H2, 02혼합가스로 열산화시켜 옅산화막을 엷은 두께로 형성하고, 이어서 화학 증착법으로 다결정 실리콘의 박막을 증착하고 화학증착법으로 제1실리콘질화막을 데포지션시키는 단계, (2) 사진식각공정을 실시하여 액티브영역과 필드영역을 구분하고 필드영역의 제1실리콘질화막, 다결정 실리론박막, 및 열산화막을 식각하여 액티브영역 패턴을 형성하는 단계. (3) 이어서 양은 두께의 2차 실리콘 질화막을 화학증착법으로 형성하고, 그위에 화학중착법으로 산화막을 데포지션하는 단계, (4) 리액티브 이온에치기술로 에치 백하여 액티브영역 패턴의 측벽에 사이드월을 형성하고, 이산화막사이드월을 마스크로하여 제2질화막을 에치하여 실리콘기판이 드러나게하는 단계, (5)산화막사이드월을 식각하여 제거하고, 채널스톱핀드 이온주입을 한스텝으로 실시하는 단계. (6) 이어서 필드산 화공정을 실시하여, 필드산화막을 형성하는 단계로 이루어진다.

Description

반도체소자의 단위소자간 격리방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 반도체소자의 단위소자간 격리방법을 설명하기위한 도면.

Claims (2)

  1. MOS형 실리콘 반도체의 소자제조공정에서 개별소자와 소자의 격리방법에 있어서. (1) 실리콘기관에 일반적인 CMOS 제조방법에 따라 원하는 농도로 도핑된 웰공정을 실시하고, 실리콘기판을 기체 02및/또는 H2, 02혼한가스로 열산화시켜 열산화막을 엷은 두께로 형성하고, 이어서 화학증착법으로 다결정 실리콘의 박막을 중착하고 화학증작법으로 제1실리콘질환막을 데포지션 시키는 단계, (2) 사진식각공정을 실시하여 액티브영역과 필드 영역을 구분하고 필드영역의 제1실리콘질화막, 다결정 실리콘박막 및 열산화막을 식각하여 액티브영역 패턴을 형성하는 단계, (3) 이어서 얇은 두께의 2차 실리콘 질화막을 화학중착법으로 형성하고, 그위에 화학증착법으로 산화막을 데포지션하는 단계, (4) 리액티브 이온에치기술로 에치백하여 액티브영역패턴의 측벽에 사이드월을 형성하고, 이산화막사이드월을 마스크로 하여 제2질화막을 에치하여 실리콘기판이 드러나게 하는 단계, (5) 산화막사이드월을 식각하여 제거하고, 채널스톱필드 이온주입을 한스텝으로 실시하는 단계, (6) 이어서 필드산화 공정을 실시하여, 필드산화막을 형성하는 단계로 이루어지는 반도체소자의 단위소자간 격리방법.
  2. 제1항에 있어서, 제4단계에서 리액티브이온에치기술로 산화막사이드월을 마스크로 하여 제2질화막과 실리콘기판 일부까지를 에치하여 실리콘기관에 얇은 홈을 형성하는 것이 특징인 반도체소자의 단위소자간 격리 방법.
    ※ 참고사항：최초출원 내용에 의하여 공개하는 것임.
KR1019920012254A 1992-07-10 1992-07-10 반도체소자의 단위소자간 격리방법 KR940003070A (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019920012254A KR940003070A (ko) 1992-07-10 1992-07-10 반도체소자의 단위소자간 격리방법
TW082104254A TW239903B (ko) 1992-07-10 1993-05-28
DE4320062A DE4320062C2 (de) 1992-07-10 1993-06-17 Verfahren zum Isolieren einzelner Elemente in einem Halbleiterchip
JP5170138A JPH06163532A (ja) 1992-07-10 1993-07-09 半導体素子分離方法
US08/089,868 US5374584A (en) 1992-07-10 1993-07-12 Method for isolating elements in a semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920012254A KR940003070A (ko) 1992-07-10 1992-07-10 반도체소자의 단위소자간 격리방법

Publications (1)

Publication Number Publication Date
KR940003070A true KR940003070A (ko) 1994-02-19

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KR1019920012254A KR940003070A (ko) 1992-07-10 1992-07-10 반도체소자의 단위소자간 격리방법

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Country Link
US (1) US5374584A (ko)
JP (1) JPH06163532A (ko)
KR (1) KR940003070A (ko)
DE (1) DE4320062C2 (ko)
TW (1) TW239903B (ko)

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KR0136518B1 (en) * 1994-04-01 1998-04-24 Hyundai Electroncis Ind Co Ltd Method for forming a field oxide layer
JPH0817813A (ja) * 1994-06-24 1996-01-19 Nec Corp 半導体装置の製造方法
DE4424015A1 (de) 1994-07-08 1996-01-11 Ant Nachrichtentech Verfahren zur Erhöhung der lateralen Unterätzung einer strukturierten Schicht
US5506169A (en) * 1994-10-20 1996-04-09 Texas Instruments Incorporated Method for reducing lateral dopant diffusion
US5629230A (en) * 1995-08-01 1997-05-13 Micron Technology, Inc. Semiconductor processing method of forming field oxide regions on a semiconductor substrate utilizing a laterally outward projecting foot portion
KR100209367B1 (ko) * 1996-04-22 1999-07-15 김영환 반도체 소자의 소자분리 절연막 형성방법
KR100439105B1 (ko) * 1997-12-31 2004-07-16 주식회사 하이닉스반도체 반도체 소자의 소자분리막 제조방법
US6214696B1 (en) * 1998-04-22 2001-04-10 Texas Instruments - Acer Incorporated Method of fabricating deep-shallow trench isolation
US6074954A (en) * 1998-08-31 2000-06-13 Applied Materials, Inc Process for control of the shape of the etch front in the etching of polysilicon
US6306726B1 (en) 1999-08-30 2001-10-23 Micron Technology, Inc. Method of forming field oxide
FR2879020B1 (fr) * 2004-12-08 2007-05-04 Commissariat Energie Atomique Procede d'isolation de motifs formes dans un film mince en materiau semi-conducteur oxydable
CN110943030A (zh) * 2018-09-21 2020-03-31 上海晶丰明源半导体股份有限公司 场氧化层结构及其制造方法

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US4508757A (en) * 1982-12-20 1985-04-02 International Business Machines Corporation Method of manufacturing a minimum bird's beak recessed oxide isolation structure
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JPS61100944A (ja) * 1984-10-22 1986-05-19 Seiko Epson Corp 半導体装置の製造方法
JPS61247051A (ja) * 1985-04-24 1986-11-04 Hitachi Ltd 半導体装置の製造方法
JPS6390150A (ja) * 1986-10-03 1988-04-21 Hitachi Ltd 半導体装置の製造方法
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Also Published As

Publication number Publication date
DE4320062A1 (de) 1994-01-13
DE4320062C2 (de) 2002-09-12
TW239903B (ko) 1995-02-01
JPH06163532A (ja) 1994-06-10
US5374584A (en) 1994-12-20

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