KR940003070A - 반도체소자의 단위소자간 격리방법 - Google Patents

반도체소자의 단위소자간 격리방법 Download PDF

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Publication number
KR940003070A
KR940003070A KR1019920012254A KR920012254A KR940003070A KR 940003070 A KR940003070 A KR 940003070A KR 1019920012254 A KR1019920012254 A KR 1019920012254A KR 920012254 A KR920012254 A KR 920012254A KR 940003070 A KR940003070 A KR 940003070A
Authority
KR
South Korea
Prior art keywords
silicon
film
etching
oxide film
sidewalls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1019920012254A
Other languages
English (en)
Korean (ko)
Inventor
이창재
양희식
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019920012254A priority Critical patent/KR940003070A/ko
Priority to TW082104254A priority patent/TW239903B/zh
Priority to DE4320062A priority patent/DE4320062C2/de
Priority to JP5170138A priority patent/JPH06163532A/ja
Priority to US08/089,868 priority patent/US5374584A/en
Publication of KR940003070A publication Critical patent/KR940003070A/ko
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
KR1019920012254A 1992-07-10 1992-07-10 반도체소자의 단위소자간 격리방법 Ceased KR940003070A (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019920012254A KR940003070A (ko) 1992-07-10 1992-07-10 반도체소자의 단위소자간 격리방법
TW082104254A TW239903B (enExample) 1992-07-10 1993-05-28
DE4320062A DE4320062C2 (de) 1992-07-10 1993-06-17 Verfahren zum Isolieren einzelner Elemente in einem Halbleiterchip
JP5170138A JPH06163532A (ja) 1992-07-10 1993-07-09 半導体素子分離方法
US08/089,868 US5374584A (en) 1992-07-10 1993-07-12 Method for isolating elements in a semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920012254A KR940003070A (ko) 1992-07-10 1992-07-10 반도체소자의 단위소자간 격리방법

Publications (1)

Publication Number Publication Date
KR940003070A true KR940003070A (ko) 1994-02-19

Family

ID=19336094

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920012254A Ceased KR940003070A (ko) 1992-07-10 1992-07-10 반도체소자의 단위소자간 격리방법

Country Status (5)

Country Link
US (1) US5374584A (enExample)
JP (1) JPH06163532A (enExample)
KR (1) KR940003070A (enExample)
DE (1) DE4320062C2 (enExample)
TW (1) TW239903B (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0136518B1 (en) * 1994-04-01 1998-04-24 Hyundai Electroncis Ind Co Ltd Method for forming a field oxide layer
JPH0817813A (ja) * 1994-06-24 1996-01-19 Nec Corp 半導体装置の製造方法
DE4424015A1 (de) 1994-07-08 1996-01-11 Ant Nachrichtentech Verfahren zur Erhöhung der lateralen Unterätzung einer strukturierten Schicht
US5506169A (en) * 1994-10-20 1996-04-09 Texas Instruments Incorporated Method for reducing lateral dopant diffusion
US5629230A (en) * 1995-08-01 1997-05-13 Micron Technology, Inc. Semiconductor processing method of forming field oxide regions on a semiconductor substrate utilizing a laterally outward projecting foot portion
KR100209367B1 (ko) * 1996-04-22 1999-07-15 김영환 반도체 소자의 소자분리 절연막 형성방법
KR100439105B1 (ko) * 1997-12-31 2004-07-16 주식회사 하이닉스반도체 반도체 소자의 소자분리막 제조방법
US6214696B1 (en) * 1998-04-22 2001-04-10 Texas Instruments - Acer Incorporated Method of fabricating deep-shallow trench isolation
US6074954A (en) * 1998-08-31 2000-06-13 Applied Materials, Inc Process for control of the shape of the etch front in the etching of polysilicon
US6306726B1 (en) 1999-08-30 2001-10-23 Micron Technology, Inc. Method of forming field oxide
FR2879020B1 (fr) * 2004-12-08 2007-05-04 Commissariat Energie Atomique Procede d'isolation de motifs formes dans un film mince en materiau semi-conducteur oxydable
CN110943030A (zh) * 2018-09-21 2020-03-31 上海晶丰明源半导体股份有限公司 场氧化层结构及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE250808C (enExample) *
GB2104722B (en) * 1981-06-25 1985-04-24 Suwa Seikosha Kk Mos semiconductor device and method of manufacturing the same
US4508757A (en) * 1982-12-20 1985-04-02 International Business Machines Corporation Method of manufacturing a minimum bird's beak recessed oxide isolation structure
JPS614240A (ja) * 1984-06-18 1986-01-10 Toshiba Corp 半導体装置の製造方法
JPS61100944A (ja) * 1984-10-22 1986-05-19 Seiko Epson Corp 半導体装置の製造方法
JPS61247051A (ja) * 1985-04-24 1986-11-04 Hitachi Ltd 半導体装置の製造方法
JPS6390150A (ja) * 1986-10-03 1988-04-21 Hitachi Ltd 半導体装置の製造方法
JPS63217640A (ja) * 1987-03-06 1988-09-09 Seiko Instr & Electronics Ltd 半導体装置の素子分離形成方法
US5149669A (en) * 1987-03-06 1992-09-22 Seiko Instruments Inc. Method of forming an isolation region in a semiconductor device
JPS63217639A (ja) * 1987-03-06 1988-09-09 Seiko Instr & Electronics Ltd 半導体装置の素子分離形成方法
JPS63253640A (ja) * 1987-04-10 1988-10-20 Toshiba Corp 半導体装置の製造方法
JPS6467938A (en) * 1987-09-09 1989-03-14 Hitachi Ltd Manufacture of semiconductor integrated circuit device
EP0424018A3 (en) * 1989-10-17 1991-07-31 American Telephone And Telegraph Company Integrated circuit field isolation process
US5248350A (en) * 1990-11-30 1993-09-28 Ncr Corporation Structure for improving gate oxide integrity for a semiconductor formed by a recessed sealed sidewall field oxidation process

Also Published As

Publication number Publication date
JPH06163532A (ja) 1994-06-10
US5374584A (en) 1994-12-20
DE4320062A1 (de) 1994-01-13
DE4320062C2 (de) 2002-09-12
TW239903B (enExample) 1995-02-01

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