KR930018703A - 반도체 리드 프레임 - Google Patents
반도체 리드 프레임Info
- Publication number
- KR930018703A KR930018703A KR1019920002797A KR920002797A KR930018703A KR 930018703 A KR930018703 A KR 930018703A KR 1019920002797 A KR1019920002797 A KR 1019920002797A KR 920002797 A KR920002797 A KR 920002797A KR 930018703 A KR930018703 A KR 930018703A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor
- lead frame
- lead
- cross
- chip bonding
- Prior art date
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
- H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
- H01L2224/06156—Covering only the central area of the surface to be connected, i.e. central arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
이 발명은 십자형태로 배열 형성된 칩 본딩 패드를 이용하여 디바이스의 신뢰성 향상 및 특성을 개선할 수 있는 반도체 리드 프레임을 개재한다
또한, 이와같이 구성된 반도체 리드 프레임은 다핀화 LOC (High pin Lead Chip)에 적용 기능하며, 반도체 리드 프레임의 설계 및 팁 패드의 배열 자유도가 증대되고, 버스바를 2개에서 4개까지 자유롭게 설계할 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 이 발명에 따른 LOC용 리드 프레임의 평면도이다.
Claims (6)
- 주변에 회로 및 여러개의 외부단자가 형성된 사각형상의 반도체 칩과, 내부리드부와 상기 내부리드부와 접속되어 있으며 내부리드에서 밀어지는 방향으로 연장하는 외부리드부로 되는 여러개의 리드와, 상기 리드의 주위에 형성된 버스바와, 상기 반도체 칩과 내부리드 사이에 개재해서 전기적으로 절연하기 위한 적어도 1개의 절연체와, 상기 외부단자와 내부리드를 전기적으로 접속하기 위한 금속와이어를 포함하는 반도체 리드 프레임으로서, 상기 외부단자와 내부리드를 전기적으로 접속하기 위하여 다수개의 칩 본딩 패드를 십자형으로 배열 형성시킨 십자형태의 칩 본딩 패드를 구비한 반도체 리드 프레임.
- 제1항에 있어서, 상기 내부리드부를 30~60°정도 경사지게 형성할 수 있도록 한 반도체 리드 프레임.
- 제1항에 있어서, 상기 버스바는 2개에서 4개 정도까지 설치할 수 있도록 한 반도체 리드 프레임.
- 제1항에 있어서, 상기 반도체 리드 프레임은 십자형 칩 본딩 패드 배열에 적합하도록 설계 및 제조할 수 있도록 한 반도체 리드 프레임.
- 제1항에 있어서, 상기 십자형태의 칩 본딩 패드는 패드의 배열 및 배치의 자유도를 크게 할 수 있도록 한 반도체 리드 프레임.
- 제1항에 있어서, 상기 십자형태의 칩 본딩 패드는 칩의 크기를 최소화시킬 수 있도록 한 반도체 리드 프레임.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920002797A KR950003908B1 (ko) | 1992-02-24 | 1992-02-24 | 반도체 리드 프레임 |
JP4306906A JP2507855B2 (ja) | 1992-02-24 | 1992-11-17 | 半導体装置 |
US08/006,202 US5250840A (en) | 1992-02-24 | 1993-01-19 | Semiconductor lead frame with a chip having bonding pads in a cross arrangement |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019920002797A KR950003908B1 (ko) | 1992-02-24 | 1992-02-24 | 반도체 리드 프레임 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR930018703A true KR930018703A (ko) | 1993-09-22 |
KR950003908B1 KR950003908B1 (ko) | 1995-04-20 |
Family
ID=19329409
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019920002797A KR950003908B1 (ko) | 1992-02-24 | 1992-02-24 | 반도체 리드 프레임 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2507855B2 (ko) |
KR (1) | KR950003908B1 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100708046B1 (ko) * | 2001-10-23 | 2007-04-16 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지용 섭스트레이트 |
-
1992
- 1992-02-24 KR KR1019920002797A patent/KR950003908B1/ko not_active IP Right Cessation
- 1992-11-17 JP JP4306906A patent/JP2507855B2/ja not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100708046B1 (ko) * | 2001-10-23 | 2007-04-16 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지용 섭스트레이트 |
Also Published As
Publication number | Publication date |
---|---|
KR950003908B1 (ko) | 1995-04-20 |
JPH05283592A (ja) | 1993-10-29 |
JP2507855B2 (ja) | 1996-06-19 |
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Legal Events
Date | Code | Title | Description |
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A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20110405 Year of fee payment: 17 |
|
EXPY | Expiration of term |