KR930017158A - 반도체 패키지 - Google Patents

반도체 패키지 Download PDF

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Publication number
KR930017158A
KR930017158A KR1019920000379A KR920000379A KR930017158A KR 930017158 A KR930017158 A KR 930017158A KR 1019920000379 A KR1019920000379 A KR 1019920000379A KR 920000379 A KR920000379 A KR 920000379A KR 930017158 A KR930017158 A KR 930017158A
Authority
KR
South Korea
Prior art keywords
semiconductor package
circuit board
printed circuit
light receiving
window frame
Prior art date
Application number
KR1019920000379A
Other languages
English (en)
Inventor
김영수
권희준
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019920000379A priority Critical patent/KR930017158A/ko
Priority to JP4313696A priority patent/JPH05259483A/ja
Publication of KR930017158A publication Critical patent/KR930017158A/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Light Receiving Elements (AREA)
  • Led Device Packages (AREA)

Abstract

이 발명은 인쇄회로기판, 윈도우 프레임과 글래스 리드를 조합하여 이미지(Image)를 촬상하는 반도체 패키지에 관한 것으로 수광소자인 포토다이오드의 투과율을 저해하지 않으며, 패키지 제조공정의 안정화및 원가절감화와 더불어 세트(set)의 실장시 실장면적을 줄이기 위한 표면실장형 패키지(Surface Mounting Package)이다.

Description

반도체 패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 이 발명에 따른 반도체 패키지의 실시예를 나타내는 단면도이고, 제3도의 (가)∼(나)는 제2도의 반도체 패키지가 인쇄회로기판에 적용되는 상태를 나타내는 평면도와 측면도이다.

Claims (8)

  1. 수광소자인 포토다이오드의 투과율을 저해하지 않도록 제작된 반도체 패키지에 있어서, 금속배선이 배치되고 양쪽에 도금단자가 형성된 인쇄회로기판과,상기 인쇄회로기판에 배치된 금속배선 사이의 소정부분에 접착제로 접착된 반도체칩과, 상기 반도체칩을 중심으로 양쪽에 형성된 윈도우 프레임과, 상기 윈도우 프레임 상단부에 형성된 글래스 리드르 구비하여 이루어짐을 특징으로 하는 반도체 패키지.
  2. 제1항에 있어서, 도금단자가 형성된 인쇄회로기판을 접촉저항이 작은금속으로 도금됨을 특징으로 하는 반도체 패키지.
  3. 제2항에 있어서, 상기 접촉저항은 작은 금속인 금(Au)등을 이용함을 특징으로 하는 반도체 패키지.
  4. 제1항에 있어서, 반도체칩에는 수광부인 포토다이오드와 칩본딩패드가 형성되어 있음을 특징으로 하는 반도체 패키지.
  5. 제1항에 있어서, 인쇄회로기판과 윈도우 프레임 접착시 사용된 접착제는 비도전성 저온경화제임을 특징으로 하는 반도체 패키지.
  6. 제5항에 있어서, 저온경화제는 150℃이하에서 접착공정을 실시함을 특징으로 하는 반도체 패키지.
  7. 제1항에 있어서, 글래스 리드와 반도체 칩의 수광부 사이가 빈 공간임을 특징으로 하는 반도체 패키지.
  8. 제1항에 있어서, 글래스 리드에는 저온경화 에폭시 접착제가 부착되어 있음을 특징으로 하는 반도체 패키지.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920000379A 1992-01-14 1992-01-14 반도체 패키지 KR930017158A (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019920000379A KR930017158A (ko) 1992-01-14 1992-01-14 반도체 패키지
JP4313696A JPH05259483A (ja) 1992-01-14 1992-11-24 光電変換用半導体パッケージ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920000379A KR930017158A (ko) 1992-01-14 1992-01-14 반도체 패키지

Publications (1)

Publication Number Publication Date
KR930017158A true KR930017158A (ko) 1993-08-30

Family

ID=19327818

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920000379A KR930017158A (ko) 1992-01-14 1992-01-14 반도체 패키지

Country Status (2)

Country Link
JP (1) JPH05259483A (ko)
KR (1) KR930017158A (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010058590A (ko) * 1999-12-30 2001-07-06 마이클 디. 오브라이언 리드 프레임을 이용한 전하결합소자용 패키지 및 그 주연리드 구조

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100359699C (zh) * 2004-12-30 2008-01-02 南亚电路板股份有限公司 互补式金属氧化物半导体影像传感器的制作方法
JP5947114B2 (ja) * 2012-06-08 2016-07-06 浜松ホトニクス株式会社 位置検出装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5139466B2 (ko) * 1971-12-23 1976-10-28
JPS5015490A (ko) * 1973-06-08 1975-02-18
JPS6027196B2 (ja) * 1980-08-08 1985-06-27 三菱電機株式会社 半導体集積回路装置
JPH02126685A (ja) * 1988-11-07 1990-05-15 Seiko Epson Corp 固体イメージセンサー

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010058590A (ko) * 1999-12-30 2001-07-06 마이클 디. 오브라이언 리드 프레임을 이용한 전하결합소자용 패키지 및 그 주연리드 구조

Also Published As

Publication number Publication date
JPH05259483A (ja) 1993-10-08

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