KR930011301A - 서브-마이크로 메터 집적회로의 얕은 접합 형성방법 - Google Patents

서브-마이크로 메터 집적회로의 얕은 접합 형성방법 Download PDF

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Publication number
KR930011301A
KR930011301A KR1019920016962A KR920016962A KR930011301A KR 930011301 A KR930011301 A KR 930011301A KR 1019920016962 A KR1019920016962 A KR 1019920016962A KR 920016962 A KR920016962 A KR 920016962A KR 930011301 A KR930011301 A KR 930011301A
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KR
South Korea
Prior art keywords
thin film
source
drain
metal
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019920016962A
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English (en)
Korean (ko)
Inventor
더블류. 리우 요우-장
나이-싱 쉔 루이스
Original Assignee
토마스 더블류. 암스트롱
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 토마스 더블류. 암스트롱, 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 토마스 더블류. 암스트롱
Publication of KR930011301A publication Critical patent/KR930011301A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/412—Deposition of metallic or metal-silicide materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
KR1019920016962A 1991-11-08 1992-09-17 서브-마이크로 메터 집적회로의 얕은 접합 형성방법 Withdrawn KR930011301A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US79073591A 1991-11-08 1991-11-08
US07/790,735 1991-11-08

Publications (1)

Publication Number Publication Date
KR930011301A true KR930011301A (ko) 1993-06-24

Family

ID=25151612

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920016962A Withdrawn KR930011301A (ko) 1991-11-08 1992-09-17 서브-마이크로 메터 집적회로의 얕은 접합 형성방법

Country Status (4)

Country Link
EP (1) EP0541212A3 (enExample)
JP (1) JPH05218075A (enExample)
KR (1) KR930011301A (enExample)
TW (1) TW201848B (enExample)

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Publication number Priority date Publication date Assignee Title
KR0138234B1 (ko) * 1994-02-24 1998-04-28 김광호 고전압 모오스 트랜지스터의 구조
US5501997A (en) * 1994-05-03 1996-03-26 United Microelectronics Corp. Process of fabricating semiconductor devices having lightly-doped drain
KR100418571B1 (ko) * 2001-06-28 2004-02-11 주식회사 하이닉스반도체 저농도 도핑 드레인 구조의 모스 트랜지스터 제조방법
US9257274B2 (en) 2010-04-15 2016-02-09 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
US9892917B2 (en) 2010-04-15 2018-02-13 Lam Research Corporation Plasma assisted atomic layer deposition of multi-layer films for patterning applications
US9373500B2 (en) 2014-02-21 2016-06-21 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
US9997357B2 (en) 2010-04-15 2018-06-12 Lam Research Corporation Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
US9611544B2 (en) 2010-04-15 2017-04-04 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9390909B2 (en) 2013-11-07 2016-07-12 Novellus Systems, Inc. Soft landing nanolaminates for advanced patterning
US8637411B2 (en) 2010-04-15 2014-01-28 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9685320B2 (en) 2010-09-23 2017-06-20 Lam Research Corporation Methods for depositing silicon oxide
US8524612B2 (en) * 2010-09-23 2013-09-03 Novellus Systems, Inc. Plasma-activated deposition of conformal films
TWI595112B (zh) 2012-10-23 2017-08-11 蘭姆研究公司 次飽和之原子層沉積及保形膜沉積
JP6538300B2 (ja) 2012-11-08 2019-07-03 ノベラス・システムズ・インコーポレーテッドＮｏｖｅｌｌｕｓ Ｓｙｓｔｅｍｓ Ｉｎｃｏｒｐｏｒａｔｅｄ 感受性基材上にフィルムを蒸着するための方法
US9214334B2 (en) 2014-02-18 2015-12-15 Lam Research Corporation High growth rate process for conformal aluminum nitride
US9478438B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method and apparatus to deposit pure titanium thin film at low temperature using titanium tetraiodide precursor
US9478411B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US10566187B2 (en) 2015-03-20 2020-02-18 Lam Research Corporation Ultrathin atomic layer deposition film accuracy thickness control
US9502238B2 (en) 2015-04-03 2016-11-22 Lam Research Corporation Deposition of conformal films by atomic layer deposition and atomic layer etch
US10526701B2 (en) 2015-07-09 2020-01-07 Lam Research Corporation Multi-cycle ALD process for film uniformity and thickness profile modulation
US9773643B1 (en) 2016-06-30 2017-09-26 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US10062563B2 (en) 2016-07-01 2018-08-28 Lam Research Corporation Selective atomic layer deposition with post-dose treatment
US10037884B2 (en) 2016-08-31 2018-07-31 Lam Research Corporation Selective atomic layer deposition for gapfill using sacrificial underlayer
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
CN114127890B (zh) 2019-05-01 2025-10-14 朗姆研究公司 调整的原子层沉积
CN114245832B (zh) 2019-06-07 2025-10-28 朗姆研究公司 原子层沉积期间的膜特性的原位控制

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4603472A (en) * 1984-04-19 1986-08-05 Siemens Aktiengesellschaft Method of making MOS FETs using silicate glass layer as gate edge masking for ion implantation
JPS61224459A (ja) * 1985-03-29 1986-10-06 Toshiba Corp 半導体装置およびその製造方法
JP2929291B2 (ja) * 1986-12-04 1999-08-03 セイコーインスツルメンツ株式会社 絶縁ゲート電界効果トランジスタの製造方法
US5166087A (en) * 1991-01-16 1992-11-24 Sharp Kabushiki Kaisha Method of fabricating semiconductor element having lightly doped drain (ldd) without using sidewalls

Also Published As

Publication number Publication date
EP0541212A2 (en) 1993-05-12
JPH05218075A (ja) 1993-08-27
TW201848B (enExample) 1993-03-11
EP0541212A3 (en) 1993-11-24

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PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

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St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

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St.27 status event code: N-1-6-B10-B12-nap-PC1203

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R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

P22-X000 Classification modified

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