KR930008971A - 반도체 장치의 층간 절연막 형성방법 - Google Patents

반도체 장치의 층간 절연막 형성방법 Download PDF

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KR930008971A
KR930008971A KR1019910019176A KR910019176A KR930008971A KR 930008971 A KR930008971 A KR 930008971A KR 1019910019176 A KR1019910019176 A KR 1019910019176A KR 910019176 A KR910019176 A KR 910019176A KR 930008971 A KR930008971 A KR 930008971A
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insulating film
interlayer insulating
bpsg
semiconductor device
concentration
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KR1019910019176A
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KR940009599B1 (ko
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김창규
홍창기
정우인
안용철
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김광호
삼성전자 주식회사
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Priority to KR1019910019176A priority Critical patent/KR940009599B1/ko
Priority to DE69227086T priority patent/DE69227086T2/de
Priority to EP92309892A priority patent/EP0540321B1/en
Priority to JP4290587A priority patent/JP2533440B2/ja
Priority to CN92112536A priority patent/CN1028817C/zh
Priority to TW081108649A priority patent/TW201363B/zh
Priority to US07/969,582 priority patent/US5405489A/en
Publication of KR930008971A publication Critical patent/KR930008971A/ko
Priority to US08/190,619 priority patent/US5652187A/en
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Publication of KR940009599B1 publication Critical patent/KR940009599B1/ko

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Abstract

반도체 소자가 서브 마이크론화 됨에 따라 열적 충격에 의한 접합 파괴가 야기되어 저온 공정 도입이 더욱 심각하게 요구된다. 특히 층간 절연막으로 이용되는 BPSG는 침적 후속공정으로 황산 보일과 리플로우를 실시하여 층간 절연막 평탄화를 달성해 왔다. 그러나 64M DRAM 이상의 미세한 소장에서는 BPSG의 저온 플로우 공정이 절실히 요구되고 있으나 BP 농도의 제한성과 황산 보일 침식으로 인하여 평탄토가 저하된다.
본 발명은 BPSG 침적 후 표면처리(M2O, N2+NH3, N2, O3, O2등 플라즈마 처리)를 실시하여 표면을 변화시킴으로써 BP 농도의 제한성을 극복하고 황산 보일이나 외부로부터 수분 흡수에 의한 침식을 제거하여 850℃ 이하의 저온 리플로우 공정을 확립하고 평탄도가 우수한 층간 절연막을 형성할 수 있다.

Description

반도체 장치의 층간 절연막 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따르는 고정 흐름도를 나타낸 도면,
제3도 내지 제4도는 본 발명에 따르는 표면처리 후의 SEM 단면도.

Claims (7)

  1. 소자가 형성된 반도체 기판을 준비하는 단계; 상기 기판 위에 고농도의 보론과 인를 함유하는 BPSG를 침적하는 단계; 사기 침적된 BPSG 표면을 플라즈마를 이용하여 표면처리를 행하는 단계; 및 저온에서 리플로우 공정을 행하는 단계로 이루어지는 것을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.
  2. 제1항에 있어서, 상기 보론의 농도는 6wt% 이상인 것을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.
  3. 제1항에 있어서, 상기 인의 농도는 6wt% 이상인 것을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.
  4. 제1항에 있어서, 상기 표면 처리용 플라즈마 가스 소스로서 N2O, N2+NH3, N2, O2, O3중 하나를 사용하는 것을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.
  5. 제1항 또는 제4항에 있어서, 상기 플라즈마 처리 조건은 온도 200℃, RF 파워 150W인 것을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.
  6. 제1항에 있어서, 상기 리플로우 공정 온도는 850℃ 이하인 것을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.
  7. 제1항에 있어서, 상기 저온 리플로우 공정전에 황산 보일로 BPSG 표면을 세정하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 층간 절연막 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910019176A 1991-10-30 1991-10-30 반도체 장치의 층간 절연막 형성방법 KR940009599B1 (ko)

Priority Applications (8)

Application Number Priority Date Filing Date Title
KR1019910019176A KR940009599B1 (ko) 1991-10-30 1991-10-30 반도체 장치의 층간 절연막 형성방법
DE69227086T DE69227086T2 (de) 1991-10-30 1992-10-28 Verfahren zur Herstellung einer dielektrischen BPSG-Zwischenschicht einer Halbleitervorrichtung
EP92309892A EP0540321B1 (en) 1991-10-30 1992-10-28 A method for fabricating an interlayer-dielectric film of BPSG in a semiconductor device
JP4290587A JP2533440B2 (ja) 1991-10-30 1992-10-29 半導体装置の層間絶縁膜形成方法
CN92112536A CN1028817C (zh) 1991-10-30 1992-10-29 半导体装置的层间绝缘膜的形成方法
TW081108649A TW201363B (ko) 1991-10-30 1992-10-30
US07/969,582 US5405489A (en) 1991-10-30 1992-10-30 Method for fabricating an interlayer-dielectric film of a semiconductor device by using a plasma treatment prior to reflow
US08/190,619 US5652187A (en) 1991-10-30 1994-02-01 Method for fabricating doped interlayer-dielectric film of semiconductor device using a plasma treatment

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KR1019910019176A KR940009599B1 (ko) 1991-10-30 1991-10-30 반도체 장치의 층간 절연막 형성방법

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KR940009599B1 KR940009599B1 (ko) 1994-10-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100462368B1 (ko) * 1996-12-28 2005-04-06 매그나칩 반도체 유한회사 반도체소자의제조방법

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5652187A (en) * 1991-10-30 1997-07-29 Samsung Electronics Co., Ltd. Method for fabricating doped interlayer-dielectric film of semiconductor device using a plasma treatment
US5474955A (en) * 1993-08-06 1995-12-12 Micron Technology, Inc. Method for optimizing thermal budgets in fabricating semconductors
JPH0817174B2 (ja) * 1993-11-10 1996-02-21 キヤノン販売株式会社 絶縁膜の改質方法
KR960019570A (ko) * 1994-11-02 1996-06-17 김주용 불순물 함유 절연막의 흡습 방지 방법
US6489255B1 (en) * 1995-06-05 2002-12-03 International Business Machines Corporation Low temperature/low dopant oxide glass film
KR0172039B1 (ko) * 1995-06-30 1999-03-30 김주용 보론 포스포러스 실리케이트 글래스막 형성방법
TW293152B (en) * 1995-07-28 1996-12-11 Hitachi Ltd Semiconductor integrated circuit device and fabricating method thereof
TW304297B (ko) * 1995-09-29 1997-05-01 Intel Corp
KR0170270B1 (ko) * 1995-12-30 1999-03-30 김광호 인규산화유리층에 형성된 콘택트 홀의 프로파일 개선 방법
US6013583A (en) * 1996-06-25 2000-01-11 International Business Machines Corporation Low temperature BPSG deposition process
US6413870B1 (en) 1996-09-30 2002-07-02 International Business Machines Corporation Process of removing CMP scratches by BPSG reflow and integrated circuit chip formed thereby
KR19980033871A (ko) * 1996-11-02 1998-08-05 김광호 반도체 장치의 제조 방법
US5913131A (en) * 1996-11-14 1999-06-15 Advanced Micro Devices, Inc. Alternative process for BPTEOS/BPSG layer formation
US5783493A (en) * 1997-01-27 1998-07-21 Taiwan Semiconductor Manufacturing Company Ltd. Method for reducing precipitate defects using a plasma treatment post BPSG etchback
GB2322734A (en) * 1997-02-27 1998-09-02 Nec Corp Semiconductor device and a method of manufacturing the same
KR100485186B1 (ko) * 1997-12-31 2005-08-24 주식회사 하이닉스반도체 반도체소자의평탄화막형성방법
US7804115B2 (en) * 1998-02-25 2010-09-28 Micron Technology, Inc. Semiconductor constructions having antireflective portions
US6274292B1 (en) * 1998-02-25 2001-08-14 Micron Technology, Inc. Semiconductor processing methods
US7314377B2 (en) * 1998-04-17 2008-01-01 Fci Americas Technology, Inc. Electrical power connector
US6281100B1 (en) 1998-09-03 2001-08-28 Micron Technology, Inc. Semiconductor processing methods
US6268282B1 (en) 1998-09-03 2001-07-31 Micron Technology, Inc. Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
CN1076763C (zh) * 1998-09-09 2001-12-26 北京航空航天大学 形状记忆合金表面绝缘膜的原位制备方法及其所制备的绝缘膜
US6828683B2 (en) 1998-12-23 2004-12-07 Micron Technology, Inc. Semiconductor devices, and semiconductor processing methods
US7235499B1 (en) 1999-01-20 2007-06-26 Micron Technology, Inc. Semiconductor processing methods
US6245688B1 (en) * 1999-05-27 2001-06-12 Taiwan Semiconductor Manufacturing Company Dry Air/N2 post treatment to avoid the formation of B/P precipitation after BPSG film deposition
US7067414B1 (en) 1999-09-01 2006-06-27 Micron Technology, Inc. Low k interlevel dielectric layer fabrication methods
US6440860B1 (en) 2000-01-18 2002-08-27 Micron Technology, Inc. Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride
DE10153176A1 (de) * 2001-08-24 2003-03-13 Schott Glas Packaging von Bauelementen mit sensorischen Eigenschaften mit einer strukturierbaren Abdichtungsschicht
DE10222964B4 (de) * 2002-04-15 2004-07-08 Schott Glas Verfahren zur Gehäusebildung bei elektronischen Bauteilen sowie so hermetisch verkapselte elektronische Bauteile
US20040261939A1 (en) * 2003-06-26 2004-12-30 Kimberly-Clark Worldwide, Inc. Cutting method and apparatus having a resilient insert
CN102479681A (zh) * 2010-11-30 2012-05-30 北大方正集团有限公司 半导体制造工艺中芯片回流的方法
US10998418B2 (en) * 2019-05-16 2021-05-04 Cree, Inc. Power semiconductor devices having reflowed inter-metal dielectric layers

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4799992A (en) * 1985-10-31 1989-01-24 Texas Instruments Incorporated Interlevel dielectric fabrication process
US4746219A (en) * 1986-03-07 1988-05-24 Texas Instruments Incorporated Local interconnect
JPS6386426A (ja) * 1986-09-30 1988-04-16 Toshiba Corp 化合物半導体装置の製造方法
US4872947A (en) * 1986-12-19 1989-10-10 Applied Materials, Inc. CVD of silicon oxide using TEOS decomposition and in-situ planarization process
JPH02181952A (ja) * 1989-01-07 1990-07-16 Sony Corp 平坦化方法
JPH04237128A (ja) * 1991-01-22 1992-08-25 Nec Corp 半導体装置の製造方法
JPH04245630A (ja) * 1991-01-31 1992-09-02 Kawasaki Steel Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100462368B1 (ko) * 1996-12-28 2005-04-06 매그나칩 반도체 유한회사 반도체소자의제조방법

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JPH05218009A (ja) 1993-08-27
CN1073551A (zh) 1993-06-23
JP2533440B2 (ja) 1996-09-11
EP0540321B1 (en) 1998-09-23
US5405489A (en) 1995-04-11
DE69227086T2 (de) 1999-04-15
EP0540321A1 (en) 1993-05-05

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