KR970023848A - 반도체장치의 제조방법 및 반도체 제조장치 - Google Patents

반도체장치의 제조방법 및 반도체 제조장치 Download PDF

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KR970023848A
KR970023848A KR1019960043611A KR19960043611A KR970023848A KR 970023848 A KR970023848 A KR 970023848A KR 1019960043611 A KR1019960043611 A KR 1019960043611A KR 19960043611 A KR19960043611 A KR 19960043611A KR 970023848 A KR970023848 A KR 970023848A
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film
reflow
plasma
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semiconductor substrate
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다케시 스나다
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니시무로 타이조
가부시키가이샤 도시바
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Abstract

반도체장치의 다층배선공정중의 층간절연막 형성공정에 리플로우 절연막 형기술을 채용한 경우에 얻어지는 리플로우 절연막의 비유전율을 높여 평탄성에 우수한 층간절연막을 평탕화 공정을 행하지 않고, 저비용으로 실현한다.
반도체기판(30) 상의 절연막(31) 상에 배선패턴(32)을 형성하는 공정과, 배선패턴 형성후의 반도체기판을 수용한 반응실 내에 SiH4가스 및 H2O2를 도입하고, 665Pa이하의 진공중에서 -10℃이상, +10℃ 이하의 온도범위에서 서로 반응시켜 리플로우형상을 갖는 리플로우 SiO2막(341)을 형성하는 리플로우막 형성공정, 이 공정에 이어 반응실에 NF3가스를 도입하고, 소정의 진공중에서 플라즈마 방전시켜 리플로우 SiO2막의 표면을 플라즈마 처리하는 플라즈마 처리공정 및, 이후 반도체기판에 대하여 소정의 열처리를 행하는 열처리공정을 구비한다.

Description

반도체장치의 제조방법 및 반도체 제조장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도4는 본 발명의 반도체장치 제조방법의 제1실시예에 따른 층간절연막 형성공정에 리플로우절연막 형성기술을 채용한 다층배선공정의 일예를 나타낸 단면도.

Claims (11)

  1. 반도체기판 상의 절연막 상에 배선패턴을 형성하는 공정과, 상기 배선패턴이 형성된 반도체기판을 수용한 반응실내에 SiH4가스 및 H2O2가스를 도입하여 약 665Pa 이하의 진공중에서 약 -10℃이상, 110℃이하의 온도범위내에서 서로 반응시켜 리플로우 형상을 갖는 리플로우 SiO2막을 형성하는 리플로우막 형성 공정, 상기 리플로우막 형성 공정에 이어 상기 반응실내에 불소계가스를 도입하여 플라즈마 방전시켜 상기 리플로우 SiO2막의 표면을 플라즈마 처리하는 플라즈마 처리공정 및, 이 후 상기 반도체기판에 대하여 열처리를 행하는 열처리공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 불소계가스로써 NF3가스, CF4가스, C2F6가스, SF6가스중 어느 하나를 사용한 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제1항 또는 제2항에 있어서, 상기 리플로우막 형성공정과 플라즈마 처리공정을 동일 반응실내에서 번갈아 복수회 실행한 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제1항에 있어서, 상기 리플로우 SiO2막을 두께(t)만큼 성막하는 공정과 이 공정에 이어 진공중에서 연속적으로 상기 불소계가스에 의한 플라즈마 표면처리를 행해 상기 두께(t)의 리플로우 SiO2막의 표면에 고농도 F층을 형성하는 공정을 x싸이클 반복하는 것에 의해 상기 리플로우 SiO2막을 막 두께(T=x, t) 성막한 것을 특징으로 하는 반도체장치의 제조방법.
  5. 제1항에 있어서, 반도체기판 상에 플라즈마 CVD법에 의해 제1플라즈마 CVD절연막을 퇴적 형성하는 공정과, 상기 리플로우막 형성공정 및, 플라즈마 처리 공정을 모두 종료한 후의 상기 반도체기판 상에 플라즈마 CVD법에 의해 제2플라즈마 CVD절연막을 퇴적 형성하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  6. 제3항에 있어서, 상기 반도체기판 상에 플라즈마 CVD법에 의해 제1플라즈마 CVD절연막을 퇴적 형성하는 공정과, 상기 리플로우막 형성공정 및, 플라즈마 처리공정을 모두 종료한 후의 상기 반도체기판 상에 플라즈마 CVD법에 의해 제2플라즈마 CVD절연막을 퇴적 형성하는 공정을 구비하여 이루어진 것을 특징으로 하는 반도체장치의 제조방법.
  7. 제5항에 있어서, 상기 플라즈마 CVD절연막 형성공정 후에 상기 열처리공정으로써 퍼니스아닐을 행함으로써, 상기 리플로우 SiO2막의 막중수분을 방출시키면서 불소를 확산시켜 SiOF를 함유하는 리플로우 SiO2막을 얻는 것을 특징으로 하는 반도체장치의 제조방법.
  8. 제6항에 있어서 상기 플라즈마 CVD절연막 형성공정 후에 상기 열처리공정으로써 퍼니스아닐을 행함으로써, 상기 리플로우 SiO2막의 막중수분을 방출시키면서 불소를 확산시켜 SiOF를 함유하는 리플로우 SiO2막을 얻는 것을 특징으로 하는 반도체장치의 제조방법.
  9. 제1항 내지 제6항중 어느 한 항에 있어서, 상기 플라즈마 처리공정은 400KHz이하주파수의 고주파전력을 사용하여 플라즈마 방전시킨 것을 특징으로 하는 반도체장치의 제조방법.
  10. 제1항 내지 제6항중 어느 한항에 있어서, 상기 플라즈마 처리공정은 400KHz 이하 주파수의 고주파전력을 사용하여 플라즈마 방전시킨 것을 특징으로 하는 반도체장치의 제조방법.
  11. 반도체 기판을 재치하기 위한 웨이퍼서셉터를 수용한 챔버내에 SiH4가스 및 H2O2가스를 도입하고, 665Pa 이하의 진공중에서 -10℃이상, +10℃이하의 온도 범위내에서 서로 반응시켜 리플로우형상을 갖는 리플로우 SiO2막을 상기 반도체기판 상에 퇴적하는 제1기능과, 상기 챔버내에 불소계가스를 도입하여 플라즈마 방전에 의해 상기 리플로우 SiO2막 표면의 플라즈마 처리를 행하는 제2기능을 구비한 감압CVD장치 및, 상기 감압CVD장치 의 제1 및 제2기능을 번갈아 선택제어하여 얻는 제어장치를 구비하여 이루어진 것을 특징으로 하는 반도체 제조장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960043611A 1995-10-03 1996-10-02 반도체장치의 제조방법 및 반도체 제조장치 KR100236205B1 (ko)

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JP3123512B2 (ja) 1998-06-02 2001-01-15 日本電気株式会社 半導体装置及びその製造方法
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US6077770A (en) * 1998-10-30 2000-06-20 United Microelectronics Corp. Damascene manufacturing process capable of forming borderless via
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JP3480416B2 (ja) 2000-03-27 2003-12-22 セイコーエプソン株式会社 半導体装置
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US9708707B2 (en) * 2001-09-10 2017-07-18 Asm International N.V. Nanolayer deposition using bias power treatment
US9121098B2 (en) 2003-02-04 2015-09-01 Asm International N.V. NanoLayer Deposition process for composite films
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