KR930005366A - 유효 데이타만을 출력하는 장치 및 방법과 메모리 장치 - Google Patents

유효 데이타만을 출력하는 장치 및 방법과 메모리 장치 Download PDF

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Publication number
KR930005366A
KR930005366A KR1019920014090A KR920014090A KR930005366A KR 930005366 A KR930005366 A KR 930005366A KR 1019920014090 A KR1019920014090 A KR 1019920014090A KR 920014090 A KR920014090 A KR 920014090A KR 930005366 A KR930005366 A KR 930005366A
Authority
KR
South Korea
Prior art keywords
buffer
data
output
memory device
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019920014090A
Other languages
English (en)
Korean (ko)
Inventor
레이 맥리란 2세 휴버트
Original Assignee
재슨 피. 디 몬트
아메리칸 텔리폰 앤드 텔레그라프 캄파니
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 재슨 피. 디 몬트, 아메리칸 텔리폰 앤드 텔레그라프 캄파니 filed Critical 재슨 피. 디 몬트
Publication of KR930005366A publication Critical patent/KR930005366A/ko
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
KR1019920014090A 1991-08-06 1992-08-06 유효 데이타만을 출력하는 장치 및 방법과 메모리 장치 Withdrawn KR930005366A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US74069591A 1991-08-06 1991-08-06
US740,695 1991-08-06

Publications (1)

Publication Number Publication Date
KR930005366A true KR930005366A (ko) 1993-03-23

Family

ID=24977648

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920014090A Withdrawn KR930005366A (ko) 1991-08-06 1992-08-06 유효 데이타만을 출력하는 장치 및 방법과 메모리 장치

Country Status (3)

Country Link
EP (1) EP0527015A2 (enrdf_load_stackoverflow)
JP (1) JPH06196997A (enrdf_load_stackoverflow)
KR (1) KR930005366A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100666931B1 (ko) * 2004-12-28 2007-01-10 주식회사 하이닉스반도체 반도체메모리소자
KR100842292B1 (ko) * 2006-12-08 2008-06-30 한국전자통신연구원 무선 공간 채널에서 수신된 데이터의 유효성 여부 판단방법 및 그 장치

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668769A (en) * 1995-11-21 1997-09-16 Texas Instruments Incorporated Memory device performance by delayed power-down
US5859985A (en) * 1996-01-14 1999-01-12 At&T Wireless Services, Inc. Arbitration controller for providing arbitration on a multipoint high speed serial bus using drivers having output enable pins
US6243782B1 (en) * 1998-12-31 2001-06-05 Intel Corporation Method and apparatus for disabling a graphics device when an upgrade device is installed
JP4551474B2 (ja) * 2006-06-30 2010-09-29 富士通株式会社 半導体集積回路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5941609B2 (ja) * 1977-08-29 1984-10-08 株式会社東芝 相補ｍｏｓ回路装置
JPS6267799A (ja) * 1985-09-20 1987-03-27 Hitachi Vlsi Eng Corp 半導体記憶装置
US4716550A (en) * 1986-07-07 1987-12-29 Motorola, Inc. High performance output driver
FR2607955B1 (fr) * 1986-12-05 1989-02-10 Eurotechnique Sa Dispositif d'autosynchronisation des circuits de sortie d'une memoire
US4858197A (en) * 1987-05-26 1989-08-15 Kabushiki Kaisha Toshiba Output buffer control circuit of memory device
US4908796A (en) * 1988-05-24 1990-03-13 Dallas Semiconductor Corporation Registered outputs for a memory device
US4972374A (en) * 1989-12-27 1990-11-20 Motorola, Inc. Output amplifying stage with power saving feature

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100666931B1 (ko) * 2004-12-28 2007-01-10 주식회사 하이닉스반도체 반도체메모리소자
KR100842292B1 (ko) * 2006-12-08 2008-06-30 한국전자통신연구원 무선 공간 채널에서 수신된 데이터의 유효성 여부 판단방법 및 그 장치

Also Published As

Publication number Publication date
EP0527015A3 (enrdf_load_stackoverflow) 1995-03-15
EP0527015A2 (en) 1993-02-10
JPH06196997A (ja) 1994-07-15

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Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 19920806

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid