KR920015601A - Cmos 및 so i 복합구조를 갖는 mos fet 생성방법 - Google Patents
Cmos 및 so i 복합구조를 갖는 mos fet 생성방법 Download PDFInfo
- Publication number
- KR920015601A KR920015601A KR1019910000486A KR910000486A KR920015601A KR 920015601 A KR920015601 A KR 920015601A KR 1019910000486 A KR1019910000486 A KR 1019910000486A KR 910000486 A KR910000486 A KR 910000486A KR 920015601 A KR920015601 A KR 920015601A
- Authority
- KR
- South Korea
- Prior art keywords
- cmos
- composites
- mos fet
- bpsg
- soi
- Prior art date
Links
- 239000002131 composite material Substances 0.000 title claims description 3
- 238000000034 method Methods 0.000 claims description 6
- 239000005380 borophosphosilicate glass Substances 0.000 claims 2
- 230000008021 deposition Effects 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 238000000465 moulding Methods 0.000 claims 1
- 150000004767 nitrides Chemical class 0.000 claims 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 따른 CMOS 및 SOI 복합구조를 갖는 MOS FET 생성방법.
Claims (1)
- MPS FET생성 공정에 있어서, 채널 스톱 I/I와 필드 산화막을 형성시키고, 질화물과 베이스 산화막을 스트립 시키고, n-도프 에피텍셜을 그로스시켜, SOI파트를 마스크 한후 에피텍셜을 식각하고, P/R을 스트립하여 게이트 산화막을 형성하여, 게이트를 패터닝하여 LDD용 S/D I/I공정과 측벽 공정을 실시하여, N+S/D I/I 및 N+S/D를 어닐시켜 P+S/D I/I공정을 행하고, 언도프 LTO디포지션을 시키고, BPSG디포지션 및 BPSG리프로우를 시키고, 컨텍 부위를 식각하여 패시베이션 후 패드 성형을 하여 CMOS 및 SOI복합구조를 갖도록 하는 것을 특징으로 하는 CMOS 및 SOI복합구조를 갖는 MOS FET 성형 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000486A KR940002776B1 (ko) | 1991-01-15 | 1991-01-15 | Cmos 및 soi 복합 구조를 갖는 mos fet 생성방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910000486A KR940002776B1 (ko) | 1991-01-15 | 1991-01-15 | Cmos 및 soi 복합 구조를 갖는 mos fet 생성방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR920015601A true KR920015601A (ko) | 1992-08-27 |
| KR940002776B1 KR940002776B1 (ko) | 1994-04-02 |
Family
ID=19309778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019910000486A KR940002776B1 (ko) | 1991-01-15 | 1991-01-15 | Cmos 및 soi 복합 구조를 갖는 mos fet 생성방법 |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR940002776B1 (ko) |
-
1991
- 1991-01-15 KR KR1019910000486A patent/KR940002776B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940002776B1 (ko) | 1994-04-02 |
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| Date | Code | Title | Description |
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| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100323 Year of fee payment: 17 |
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| EXPY | Expiration of term |