KR920015451A - 트랜지스터의 격리층 형성방법 - Google Patents

트랜지스터의 격리층 형성방법 Download PDF

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Publication number
KR920015451A
KR920015451A KR1019910000841A KR910000841A KR920015451A KR 920015451 A KR920015451 A KR 920015451A KR 1019910000841 A KR1019910000841 A KR 1019910000841A KR 910000841 A KR910000841 A KR 910000841A KR 920015451 A KR920015451 A KR 920015451A
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KR
South Korea
Prior art keywords
silicon oxide
oxide film
film
isolation layer
bsg
Prior art date
Application number
KR1019910000841A
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English (en)
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KR100205435B1 (ko
Inventor
김희석
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910000841A priority Critical patent/KR100205435B1/ko
Publication of KR920015451A publication Critical patent/KR920015451A/ko
Application granted granted Critical
Publication of KR100205435B1 publication Critical patent/KR100205435B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

내용 없음

Description

트랜지스터의 격리층 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 제조공정 단면도.

Claims (1)

  1. 기판상에 기판과 다른형의 에피층을 성장시킨 다음 제1실리콘 산화막을 형성하는 단계, 상기 제1실리콘 산화막상에 포토/에치 공정을 실시하여 격리층이 형성될 영역에 트렌치를 형성하는 단계, 전체적으로 BSG막을 소정두께로 도포하고 상기 제1실리콘 산화막을 소킹하여 BSG막의 보론이온을 상기 에피층에 확산시킴으로써 상기 트렌치 하층에 P+형 격리영역을 형성하는 단게, 상기 BSG막을 제거하고 상기 P+형 격리영역과 제1실리콘산화막상에 저온산화를 실시하여 제2실리콘 산화막을 형성하는 단계, 잔여 BSG막을 제거하는 단계가 차례로 포함됨을 특징으로 하는 트랜지스터의 격리층 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910000841A 1991-01-18 1991-01-18 트랜지스터의 격리층 형성방법 KR100205435B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910000841A KR100205435B1 (ko) 1991-01-18 1991-01-18 트랜지스터의 격리층 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910000841A KR100205435B1 (ko) 1991-01-18 1991-01-18 트랜지스터의 격리층 형성방법

Publications (2)

Publication Number Publication Date
KR920015451A true KR920015451A (ko) 1992-08-26
KR100205435B1 KR100205435B1 (ko) 1999-07-01

Family

ID=19310034

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910000841A KR100205435B1 (ko) 1991-01-18 1991-01-18 트랜지스터의 격리층 형성방법

Country Status (1)

Country Link
KR (1) KR100205435B1 (ko)

Also Published As

Publication number Publication date
KR100205435B1 (ko) 1999-07-01

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