KR940010381A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

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Publication number
KR940010381A
KR940010381A KR1019920019345A KR920019345A KR940010381A KR 940010381 A KR940010381 A KR 940010381A KR 1019920019345 A KR1019920019345 A KR 1019920019345A KR 920019345 A KR920019345 A KR 920019345A KR 940010381 A KR940010381 A KR 940010381A
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KR
South Korea
Prior art keywords
semiconductor device
junction
film
sio
present
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Application number
KR1019920019345A
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English (en)
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KR100268860B1 (ko
Inventor
이창재
김재정
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019920019345A priority Critical patent/KR100268860B1/ko
Publication of KR940010381A publication Critical patent/KR940010381A/ko
Application granted granted Critical
Publication of KR100268860B1 publication Critical patent/KR100268860B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

Abstract

본 발명은 반도체 장치의 제조시에 소오스/드레인 접합을 얇게 하는 접합형성 방법에 관한 것으로서, 본 발명의 효과로는 접합형성시에 실리콘 이온주입을 실리콘 기판에 직접하지 않음으로서 열처리시 결정결함을 최소화 할 수 있고, 기판으로의 도팬트 확산을 방지할 수 있어서 접합깊이를 더욱 얇게 만들 수가 있고, 원하는 농도의 프로파일 제어를 용이하게 할 수 있다.

Description

반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따라 반도체장치 제조시의 접합공정도.

Claims (1)

  1. 반도체 기판상에 절연막(3), 게이트(4) 및 SiO2막(5)을 형성한 후 에치백하여 SiO2측벽(6a,6b)를 형성하는 단계와, 상기 SiO2막(5)위에 소정두께의 비정질실리콘막(7)을 증착한 후, 실리콘 이온을 주입하는 단계와, 소오스/드레인은 형성하기 위한 도팬트를 이온주입한 후 열처리를 행하는 단계를 구비한 것은 특징으로 하는 반도체장치의 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920019345A 1992-10-21 1992-10-21 반도체 장치의 제조방법 KR100268860B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920019345A KR100268860B1 (ko) 1992-10-21 1992-10-21 반도체 장치의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920019345A KR100268860B1 (ko) 1992-10-21 1992-10-21 반도체 장치의 제조방법

Publications (2)

Publication Number Publication Date
KR940010381A true KR940010381A (ko) 1994-05-26
KR100268860B1 KR100268860B1 (ko) 2000-10-16

Family

ID=19341494

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920019345A KR100268860B1 (ko) 1992-10-21 1992-10-21 반도체 장치의 제조방법

Country Status (1)

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KR (1) KR100268860B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100321925B1 (ko) * 1998-11-26 2002-10-25 삼성전자 주식회사 4장의마스크를이용한액정표시장치용박막트랜지스터기판의제조방법및액정표시장치용박막트랜지스터기판

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02244715A (ja) * 1989-03-17 1990-09-28 Kawasaki Steel Corp 半導体装置の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100321925B1 (ko) * 1998-11-26 2002-10-25 삼성전자 주식회사 4장의마스크를이용한액정표시장치용박막트랜지스터기판의제조방법및액정표시장치용박막트랜지스터기판

Also Published As

Publication number Publication date
KR100268860B1 (ko) 2000-10-16

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