KR920010848A - 패키지 형성공정 - Google Patents

패키지 형성공정 Download PDF

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Publication number
KR920010848A
KR920010848A KR1019900018359A KR900018359A KR920010848A KR 920010848 A KR920010848 A KR 920010848A KR 1019900018359 A KR1019900018359 A KR 1019900018359A KR 900018359 A KR900018359 A KR 900018359A KR 920010848 A KR920010848 A KR 920010848A
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South Korea
Prior art keywords
package
forming process
package forming
manufacturing
molding
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KR1019900018359A
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English (en)
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KR940002444B1 (ko
Inventor
고준수
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문정환
금성일렉트론 주식회사
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Priority to KR1019900018359A priority Critical patent/KR940002444B1/ko
Priority to DE4135189A priority patent/DE4135189B4/de
Priority to US07/787,484 priority patent/US5200367A/en
Priority to JP3297355A priority patent/JPH05291426A/ja
Publication of KR920010848A publication Critical patent/KR920010848A/ko
Application granted granted Critical
Publication of KR940002444B1 publication Critical patent/KR940002444B1/ko

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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Moulds, Cores, Or Mandrels (AREA)

Abstract

내용 없음

Description

패키지 형성공정
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 1차 몰딩공정을 나타낸 개략도, 제3도는 본 발명의 2차 몰딩공정을 나타낸 개략도.

Claims (2)

  1. 2중 몰딩에 의한 패키지 형상을 제조하고 다이부착공정, 와이어 본딩공정, 밀봉공정을 차례로 실시함을 특징으로하는 패키지 형성공정.
  2. 제1항에 있어서, 2중 몰딩공정은 세라믹 패키지의 패턴형성을 위해 리드프레임의 이너리드 부분을 먼저 몰딩하고 고정시키고 이어서 패키지 외형에 맞게 몰드금형을 제조하여 패키지를 형성시킴을 특징으로 하는 패키지 형성공정.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900018359A 1990-11-13 1990-11-13 반도체 소자의 패키지 어셈블리 방법 KR940002444B1 (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1019900018359A KR940002444B1 (ko) 1990-11-13 1990-11-13 반도체 소자의 패키지 어셈블리 방법
DE4135189A DE4135189B4 (de) 1990-11-13 1991-10-24 Verfahren zur Montage des Gehäuses eines Halbleiter-Bauelements
US07/787,484 US5200367A (en) 1990-11-13 1991-11-06 Method for assembling packages of semi-conductor elements
JP3297355A JPH05291426A (ja) 1990-11-13 1991-11-13 半導体素子パッケージの組立方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900018359A KR940002444B1 (ko) 1990-11-13 1990-11-13 반도체 소자의 패키지 어셈블리 방법

Publications (2)

Publication Number Publication Date
KR920010848A true KR920010848A (ko) 1992-06-27
KR940002444B1 KR940002444B1 (ko) 1994-03-24

Family

ID=19305981

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900018359A KR940002444B1 (ko) 1990-11-13 1990-11-13 반도체 소자의 패키지 어셈블리 방법

Country Status (4)

Country Link
US (1) US5200367A (ko)
JP (1) JPH05291426A (ko)
KR (1) KR940002444B1 (ko)
DE (1) DE4135189B4 (ko)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940001333A (ko) * 1992-06-16 1994-01-11 문정환 수지봉합형 고체촬상소자 패키지 및 그 제조방법
JP2888040B2 (ja) * 1992-07-10 1999-05-10 日本電気株式会社 半導体装置およびその製造方法
US5337217A (en) * 1993-02-25 1994-08-09 Eastman Kodak Company Integrated circuit package for an image sensor
KR970005706B1 (ko) * 1994-01-24 1997-04-19 금성일렉트론 주식회사 고체촬상소자 및 그 제조방법
NL9400766A (nl) * 1994-05-09 1995-12-01 Euratec Bv Werkwijze voor het inkapselen van een geintegreerde halfgeleiderschakeling.
US5766975A (en) * 1995-01-09 1998-06-16 Integrated Device Technology, Inc. Packaged integrated circuit having thermal enhancement and reduced footprint size
DE19530577B4 (de) * 1995-08-19 2005-03-10 Conti Temic Microelectronic Gehäuse für mikroelektronische Bauelemente und Verfahren zu seiner Herstellung
MY128748A (en) * 1995-12-19 2007-02-28 Texas Instruments Inc Plastic packaging for a surface mounted integrated circuit
WO1999000852A1 (fr) * 1997-06-27 1999-01-07 Iwasaki Electric Co., Ltd. Diode electroluminescente de type reflechissante
TW360935B (en) * 1997-11-14 1999-06-11 Amic Technology Inc Variable package structure and process for producing the same
JP3543189B2 (ja) * 1997-12-10 2004-07-14 日本オプネクスト株式会社 半導体素子パッケージおよび半導体装置
JP2002134762A (ja) * 2000-10-19 2002-05-10 Shinko Electric Ind Co Ltd 光学装置及びその製造方法
US6703700B2 (en) * 2001-10-12 2004-03-09 Cheng-Ho Hsu Semiconductor packaging structure
DE10221857A1 (de) * 2002-05-16 2003-11-27 Osram Opto Semiconductors Gmbh Verfahren zum Befestigen eines Halbleiterchips in einem Kunststoffgehäusekörper, optoelektronisches Halbleiterbauelement und Verfahren zu dessen Herstellung
US6953291B2 (en) * 2003-06-30 2005-10-11 Finisar Corporation Compact package design for vertical cavity surface emitting laser array to optical fiber cable connection
DE10348253B3 (de) * 2003-10-16 2005-02-17 Robert Bosch Gmbh Verfahren zum Einkleben eines Chips in ein Premold-Gehäuse und zugehöringe Vorrichtung
EP1628338A1 (en) * 2004-08-19 2006-02-22 Optimum Care International Tech. Inc. The manufacturing method of a modularized leadframe
US20090160047A1 (en) * 2007-12-21 2009-06-25 Schlumberger Technology Corporation Downhole tool
TWM440524U (en) 2012-02-21 2012-11-01 Domintech Co Ltd Semiconductor package with a base
JP5885690B2 (ja) 2012-04-27 2016-03-15 キヤノン株式会社 電子部品および電子機器
JP2013243340A (ja) * 2012-04-27 2013-12-05 Canon Inc 電子部品、実装部材、電子機器およびこれらの製造方法
JP6296687B2 (ja) 2012-04-27 2018-03-20 キヤノン株式会社 電子部品、電子モジュールおよびこれらの製造方法。
US20140377915A1 (en) * 2013-06-20 2014-12-25 Infineon Technologies Ag Pre-mold for a magnet semiconductor assembly group and method of producing the same
JP2015038920A (ja) * 2013-08-19 2015-02-26 ソニー株式会社 撮像装置および電子機器
JP6392654B2 (ja) * 2014-02-04 2018-09-19 エイブリック株式会社 光センサ装置
CN105300593B (zh) * 2014-07-28 2018-12-28 恩智浦美国有限公司 具有盖的封装的半导体传感器装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5386576A (en) * 1977-01-10 1978-07-31 Nec Corp Package for semiconductor element
JPS593857B2 (ja) * 1979-04-26 1984-01-26 三菱電機株式会社 半導体装置
JPS584957A (ja) * 1982-06-22 1983-01-12 Nec Kyushu Ltd 半導体装置
JPS5996749A (ja) * 1982-11-25 1984-06-04 Matsushita Electric Works Ltd 樹脂封止型電子部品の製造方法
DD221601A1 (de) * 1983-09-02 1985-04-24 Funkwerk Erfurt Veb K Verfahren zum herstellen kunststoffverkappter hochpoliger integrierter schaltkreise
JPS60239043A (ja) * 1984-05-14 1985-11-27 Oki Electric Ind Co Ltd 半導体装置用パツケ−ジの製造方法
JPS60257546A (ja) * 1984-06-04 1985-12-19 Mitsubishi Electric Corp 半導体装置及びその製造方法
US4649415A (en) * 1985-01-15 1987-03-10 National Semiconductor Corporation Semiconductor package with tape mounted die
IT1186165B (it) * 1985-12-20 1987-11-18 Sgs Microelettronica Spa Dispositivo a semiconduttore di tipo eprom cancellabile con raggi ultravioletti e suo processo di fabbricazione
FR2598258B1 (fr) * 1986-04-30 1988-10-07 Aix Les Bains Composants Procede d'encapsulation de circuits integres.
JP2674701B2 (ja) * 1986-05-01 1997-11-12 日東電工株式会社 半導体装置
US4812420A (en) * 1986-09-30 1989-03-14 Mitsubishi Denki Kabushiki Kaisha Method of producing a semiconductor device having a light transparent window
US4761518A (en) * 1987-01-20 1988-08-02 Olin Corporation Ceramic-glass-metal packaging for electronic components incorporating unique leadframe designs
US4833102A (en) * 1987-03-17 1989-05-23 National Semiconductor Corporation Process of making a ceramic lid for use in a hermetic seal package
JP2579315B2 (ja) * 1987-06-17 1997-02-05 新光電気工業株式会社 セラミツクパツケ−ジ
JPS6411352A (en) * 1987-07-06 1989-01-13 Sony Corp Hollow mold package
US4837184A (en) * 1988-01-04 1989-06-06 Motorola Inc. Process of making an electronic device package with peripheral carrier structure of low-cost plastic
JPH01228152A (ja) * 1988-03-09 1989-09-12 Hitachi Chem Co Ltd 半導体装置の製造方法
KR970011649B1 (ko) * 1988-03-10 1997-07-12 가부시끼가이샤 히다찌세이사꾸쇼 반도체 장치의 제조방법

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DE4135189B4 (de) 2006-03-02
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US5200367A (en) 1993-04-06
KR940002444B1 (ko) 1994-03-24

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