KR920010761A - 반도체소자실장방법 - Google Patents

반도체소자실장방법 Download PDF

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KR920010761A
KR920010761A KR1019910020651A KR910020651A KR920010761A KR 920010761 A KR920010761 A KR 920010761A KR 1019910020651 A KR1019910020651 A KR 1019910020651A KR 910020651 A KR910020651 A KR 910020651A KR 920010761 A KR920010761 A KR 920010761A
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semiconductor device
mounting method
device mounting
wiring board
heat dissipation
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KR1019910020651A
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KR960000696B1 (ko
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마사노리 니시구찌
아쯔시 미끼
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쿠라우찌 노리타카
스미도모덴기고오교오 가부시기가이샤
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Priority claimed from JP2312667A external-priority patent/JPH04184952A/ja
Priority claimed from JP2312666A external-priority patent/JPH04184951A/ja
Priority claimed from JP2312665A external-priority patent/JPH04184950A/ja
Application filed by 쿠라우찌 노리타카, 스미도모덴기고오교오 가부시기가이샤 filed Critical 쿠라우찌 노리타카
Publication of KR920010761A publication Critical patent/KR920010761A/ko
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Publication of KR960000696B1 publication Critical patent/KR960000696B1/ko

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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Abstract

내용 없음

Description

반도체소자실장방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 반도체소자실장방법에 대한 설명도,
제2도 및 제3도는 본 발명의 제2실시예에 따른 반도체소자실장방법에 대한 설명도로서,
제2도는 반도체소자를 히이트싱크에 접착하는 공정을 도시한 도면이고,
제3도는 반도체소자를 배선기판에 페이스다운본딩하는 공정을 도시한 도면.

Claims (9)

  1. 각각 범프전극을 가지는 복수의 반도체소자를 준비하는 공정과, 상기 반도체소자의 범프전극을 형성한 표면과 반대쪽의 이면에 방열수단을 접착하는 공정과, 범프전극을 위치맞춤시켜 상기 반도체소자를 배선기판에 밀어붙이는 공정과, 상기 배선기판상에 상기 반도체소자를 가열해서 실장하는 공정으로 구성된 반도체소자실장방법.
  2. 제1항에 있어서, 상기 방렬수단이 상기 각각의 반도체소장에 대응하는 복수의 히이트싱크를 포함하는 것을 특징으로 하는 반도체소자실장방법.
  3. 제1항에 있어서, 상기 가열공정후에, 상기 배선기판, 상기 반도체소자 및 상기 방열수단과의 사이에 성형수지를 형성하는 공정을 포함하는 것을 특징으로 하는 반도체소자실장방법.
  4. 제1항에 있어서, 상기 방열수단이 하나의 히이트싱크를 포함하는 것을 특징으로 하는 반도체소자실장방법.
  5. 제1항에 있어서, 상기 배선기판의 전극이 볼록형상으로 형성되어 있는 것을 특징으로 하는 반도체소자실장방법.
  6. 제1항에 있어서, 상기 접착공정전에 상기 방열수단상에 레지스트패턴을 형성하여 상기 반도체소자를 위치맞춤하는 공정을 포함하는 것을 특징으로 하는 반도체소자실장방법.
  7. 제4항에 있어서, 상기 접착공정전에 상기 히이트싱크의 하부면상에 레지스트패턴을 형성하여 상기 반도체소자를 위치맞춤하는 공정을 포함하는 것을 특징으로 하는 반도체소자실장방법.
  8. 제1항에 있어서, 상기 배선기판의 전극이 오목형상으로 형성되어 있는 것을 특징으로 하는 반도체소자실장방법.
  9. 제8항에 있어서, 상기 범프재료보다 융점이 낮은 땜납을 사용하여 상기 반도체소자를 상기 방열수단에 접착하는 것을 특징으로 하는 반도체소자실장방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910020651A 1990-11-20 1991-11-20 반도체소자실장방법 KR960000696B1 (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2312667A JPH04184952A (ja) 1990-11-20 1990-11-20 半導体素子実装方法
JP2312666A JPH04184951A (ja) 1990-11-20 1990-11-20 半導体素子実装方法
JP90-312666 1990-11-20
JP2312665A JPH04184950A (ja) 1990-11-20 1990-11-20 半導体素子実装方法
JP90-312667 1990-11-20
JP90-312665 1990-11-20

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Publication Number Publication Date
KR920010761A true KR920010761A (ko) 1992-06-27
KR960000696B1 KR960000696B1 (ko) 1996-01-11

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EP (1) EP0490125B1 (ko)
KR (1) KR960000696B1 (ko)
AU (1) AU640537B2 (ko)
CA (1) CA2055845A1 (ko)
DE (1) DE69117891T2 (ko)

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AU640537B2 (en) 1993-08-26
DE69117891T2 (de) 1996-07-25
DE69117891D1 (de) 1996-04-18
EP0490125B1 (en) 1996-03-13
AU8799891A (en) 1992-05-21
US5244142A (en) 1993-09-14
EP0490125A1 (en) 1992-06-17
CA2055845A1 (en) 1992-05-21
US5348214A (en) 1994-09-20
KR960000696B1 (ko) 1996-01-11

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