KR970023906A - Pcb 기판 형성방법 및 그를 이용한 bga 반도체 패키지 구조 - Google Patents

Pcb 기판 형성방법 및 그를 이용한 bga 반도체 패키지 구조 Download PDF

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KR970023906A
KR970023906A KR1019950036141A KR19950036141A KR970023906A KR 970023906 A KR970023906 A KR 970023906A KR 1019950036141 A KR1019950036141 A KR 1019950036141A KR 19950036141 A KR19950036141 A KR 19950036141A KR 970023906 A KR970023906 A KR 970023906A
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South Korea
Prior art keywords
semiconductor package
package structure
heat sink
pcb
bga semiconductor
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KR1019950036141A
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English (en)
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KR100258606B1 (ko
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허영욱
이무응
배동주
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황인길
아남산업주식회사
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Publication of KR970023906A publication Critical patent/KR970023906A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

본 발명은 PCB 기판 형성방법 및 그를 이용한 BGA반도체 패키지 구조에 관한 것으로, PCB기판의 상면에 솔더볼이 부착되고, 그 저면에 열 전도성이 우수한 히트싱크를 접착하되, 상기 PCB기판에는 히트싱크에 직접 반도체 칩이 접착되도록 하기 위하여 구멍(Cavity)을 형성하여 이 구멍을 통해 히트싱크에 작접 반도체 칩을 부착하여 반도체 칩에서 발생되는 열의 방출을 극대화 시키도록 하여 반도체 칩의 성능을 최대한 발휘할수 있도록 한 PCB 기판 형성방법 및 그를 이용한 BGA 반도체 패키지 구조이다.

Description

PCB 기관 형성방법 및 그를 이용한 BGA 반도체 패키지 구조
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 의한 BGA 반도체 패키지의 구조를 보인 단면도.
제4도는 본 발명에 따른 PCB기판의 공정상태를 나타낸 도면.

Claims (9)

  1. BGA 반도체 패키지를 구성함에 있어서, PCB기판의 상면에 솔더 볼이 부착되고, 그 저면에 열 전도성이 우수한 히트싱크를 접착하되, 상기 PGB기판에는 히트싱크에 직접 반도체 칩이 접착되도록 하기 위하여 구멍(Cavity)을 형성하여 이 구멍을 통해 히트싱크에 직접 반도체 칩을 부착한 것을 특징으로 하는 BGA반도체 패키지 구조.
  2. 제1항에 있어서, 상기 히트싱크는 구리 또는 알루미늄으로 된것을 특징으로 BGA반도체 패키지 구조.
  3. 제1항에 있어서, 상기 히트싱크는 반도체 칩이 부착되는 표면에는 PCB기판과의 접착강도를 높이기 위하여 흑색 산화물(Black oxide)을 처리하여서 된 것을 특징으로 하는 BGA반도체 패키지 구조.
  4. 제1항에 있어서, 상기 히트싱크는 외부로 노출되는 표면에 니켈(Ni)도금 하여서 된 것을 특징으로 하는 BGA반도체 패키지 구조.
  5. 제1항에 있어서, 상기 PCB기판에 관통슬롯을 형성하여 히트싱크와 연결되도록 된 것을 특징으로 하는 BGA반도체 패키지 구조.
  6. 제1항에 있어서, 상기 반도체 칩은 액체 타입의 글로우브(Globe)로 몰딩된 것을 특징으로 하는 BGA 반도체 패키지 구조.
  7. 제1항에 있어서, 상기 PCB기판의 구멍 주변에 와이어의 다운 본드(Down Bond)을 위해 그라운드(Ground)및 파우어 링(Power Ring)이 형성된 것을 특징으로 하는 BGA 반도체 패키지 구조.
  8. 일면 또는 양면에 원하는 회로 패턴(Pattern)을 형성하고, 회로 패턴 상부에 니켈(Ni) 또는 금(Au)도금을 입힌 다음, 솔더 마스크를 일면 또는 양면에 입혀 PCB패널을 형성하는 단계와, 상기 PCB패널에 반도체 칩이 장착되는 부분에 구멍(Cavity)을 형성하는 단계와, 상기 구멍을 형성한 PCB패널의 일측면에 열 전도성이 우수한 히트싱크를 접착 테이프를 이용하여 접착시키는 단계와, 상기 단계를 거친 PCB패널을 제조공정이 용이하도록 스트립 타입(Strip Type) 또는, 싱글 타입(Single Type)으로 절단하는 단계로 이루어진 것은 특징으로 하는 PCB 기판 형성방법.
  9. 제8항에 있어서, 상기 PCB패널은 펀치 공구, 레이져 또는 소잉(Sawing)장비로 절단하는 것을 특징으로 하는 PCB 기판 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950036141A 1995-10-19 1995-10-19 Pcb 기판 형성방법 및 그를 이용한 bga 반도체 패키지 구조 KR100258606B1 (ko)

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KR1019950036141A KR100258606B1 (ko) 1995-10-19 1995-10-19 Pcb 기판 형성방법 및 그를 이용한 bga 반도체 패키지 구조

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KR1019950036141A KR100258606B1 (ko) 1995-10-19 1995-10-19 Pcb 기판 형성방법 및 그를 이용한 bga 반도체 패키지 구조

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KR970023906A true KR970023906A (ko) 1997-05-30
KR100258606B1 KR100258606B1 (ko) 2000-06-15

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010057046A (ko) * 1999-12-17 2001-07-04 이형도 캐비티를 갖는 패키지 기판
KR100443399B1 (ko) * 2001-10-25 2004-08-09 삼성전자주식회사 보이드가 형성된 열 매개 물질을 갖는 반도체 패키지
KR100471413B1 (ko) * 2002-03-27 2005-02-21 주식회사 칩팩코리아 테이프 볼 그리드 어레이 패키지

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030066996A (ko) * 2002-02-06 2003-08-14 주식회사 칩팩코리아 향상된 열방출 특성을 갖는 볼 그리드 어레이 패키지
KR20040032474A (ko) * 2002-10-10 2004-04-17 (주)동양기연 반도체 패키지 실장용 방열판
KR100480834B1 (ko) * 2002-11-27 2005-04-07 앰코 테크놀로지 코리아 주식회사 레이저 마킹용 영구 테이프구조

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010057046A (ko) * 1999-12-17 2001-07-04 이형도 캐비티를 갖는 패키지 기판
KR100443399B1 (ko) * 2001-10-25 2004-08-09 삼성전자주식회사 보이드가 형성된 열 매개 물질을 갖는 반도체 패키지
KR100471413B1 (ko) * 2002-03-27 2005-02-21 주식회사 칩팩코리아 테이프 볼 그리드 어레이 패키지

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