KR920007164A - 다층 리드프레임 - Google Patents

다층 리드프레임 Download PDF

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Publication number
KR920007164A
KR920007164A KR1019910015414A KR910015414A KR920007164A KR 920007164 A KR920007164 A KR 920007164A KR 1019910015414 A KR1019910015414 A KR 1019910015414A KR 910015414 A KR910015414 A KR 910015414A KR 920007164 A KR920007164 A KR 920007164A
Authority
KR
South Korea
Prior art keywords
lead frame
metal
semiconductor chip
laminated
outer circumferential
Prior art date
Application number
KR1019910015414A
Other languages
English (en)
Other versions
KR950001369B1 (ko
Inventor
미쓰하루 시미즈
히로후미 후지이
요시끼 다까다
Original Assignee
이노우에 사다오
신꼬오 덴기 고오교오 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이노우에 사다오, 신꼬오 덴기 고오교오 가부시끼가이샤 filed Critical 이노우에 사다오
Publication of KR920007164A publication Critical patent/KR920007164A/ko
Application granted granted Critical
Publication of KR950001369B1 publication Critical patent/KR950001369B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49527—Additional leads the additional leads being a multilayer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용없음.

Description

다층 리드프레임
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 다층 리드프레임에 반도체 칩을 탑재한 실시예의 설명도.
제2도는 프레스버(press burr)의 발생상태를 나타낸 설명도.
제3도는 다층 리드프레임의 종례예를 나타낸 설명도.

Claims (2)

  1. 인너리드와 1매 또는 복수매의 금속플레인을 전기적 절연층을 중간에 개재시켜서 적층한 다층 리드프레임에 있어서, 리드프레임에 탑재되는 반도체 칩에 대면되는 상기 인너리드의 전단면위치 및 상기 금속플레인의 전단면 위치보다도 상기 전기적 절연층의 전단면을 반도체 칩쪽으로 전진시킨 것을 특징으로 하는 다층 리드프레임.
  2. 인너리드와 1매 또는 복수매의 금속플레인을 전기적 절연층을 중간에 개재시켜 적층한 다음 리드프레임에 있어서, 상기 전기적 절연층의 외주 치수를 상기 금속플레인의 외주 치수보다도 크게한 것을 특징으로 하는 다층 리드프레임.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019910015414A 1990-09-04 1991-09-04 다층 리드프레임 KR950001369B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2-235067 1990-09-04
JP1990-235067 1990-09-04
JP2235067A JP2966067B2 (ja) 1990-09-04 1990-09-04 多層リードフレーム

Publications (2)

Publication Number Publication Date
KR920007164A true KR920007164A (ko) 1992-04-28
KR950001369B1 KR950001369B1 (ko) 1995-02-17

Family

ID=16980581

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910015414A KR950001369B1 (ko) 1990-09-04 1991-09-04 다층 리드프레임

Country Status (6)

Country Link
US (1) US5235209A (ko)
EP (1) EP0474469B1 (ko)
JP (1) JP2966067B2 (ko)
KR (1) KR950001369B1 (ko)
DE (1) DE69125072T2 (ko)
HK (1) HK1001575A1 (ko)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5556807A (en) * 1992-02-18 1996-09-17 Intel Corporation Advance multilayer molded plastic package using mesic technology
JPH0653277A (ja) * 1992-06-04 1994-02-25 Lsi Logic Corp 半導体装置アセンブリおよびその組立方法
US5854094A (en) * 1992-07-28 1998-12-29 Shinko Electric Industries Co., Ltd. Process for manufacturing metal plane support for multi-layer lead frames
US5777265A (en) * 1993-01-21 1998-07-07 Intel Corporation Multilayer molded plastic package design
JP2931741B2 (ja) * 1993-09-24 1999-08-09 株式会社東芝 半導体装置
US5343074A (en) * 1993-10-04 1994-08-30 Motorola, Inc. Semiconductor device having voltage distribution ring(s) and method for making the same
US5578869A (en) * 1994-03-29 1996-11-26 Olin Corporation Components for housing an integrated circuit device
JP2536459B2 (ja) * 1994-09-26 1996-09-18 日本電気株式会社 半導体装置及びその製造方法
GB2293918A (en) * 1994-10-06 1996-04-10 Ibm Electronic circuit packaging
US5965936A (en) 1997-12-31 1999-10-12 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device
KR100253028B1 (ko) * 1994-11-10 2000-04-15 로데릭 더블류 루이스 반도체장치용다층리드프레임
US5818114A (en) * 1995-05-26 1998-10-06 Hewlett-Packard Company Radially staggered bond pad arrangements for integrated circuit pad circuitry
GB9515651D0 (en) * 1995-07-31 1995-09-27 Sgs Thomson Microelectronics A method of manufacturing a ball grid array package
US6054754A (en) 1997-06-06 2000-04-25 Micron Technology, Inc. Multi-capacitance lead frame decoupling device
US6515359B1 (en) 1998-01-20 2003-02-04 Micron Technology, Inc. Lead frame decoupling capacitor semiconductor device packages including the same and methods
US6114756A (en) 1998-04-01 2000-09-05 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit leadframes
US6414386B1 (en) * 2000-03-20 2002-07-02 International Business Machines Corporation Method to reduce number of wire-bond loop heights versus the total quantity of power and signal rings
KR20030066994A (ko) * 2002-02-06 2003-08-14 주식회사 칩팩코리아 다층 리드프레임 및 이를 이용한 칩 사이즈 패키지
US8354743B2 (en) * 2010-01-27 2013-01-15 Honeywell International Inc. Multi-tiered integrated circuit package
US9741644B2 (en) 2015-05-04 2017-08-22 Honeywell International Inc. Stacking arrangement for integration of multiple integrated circuits

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61108160A (ja) * 1984-11-01 1986-05-26 Nec Corp コンデンサ内蔵型半導体装置及びその製造方法
GB2174538A (en) * 1985-04-24 1986-11-05 Stanley Bracey Semiconductor package
JP2734463B2 (ja) * 1989-04-27 1998-03-30 株式会社日立製作所 半導体装置
JP2744685B2 (ja) * 1990-08-08 1998-04-28 三菱電機株式会社 半導体装置

Also Published As

Publication number Publication date
JPH04114461A (ja) 1992-04-15
US5235209A (en) 1993-08-10
HK1001575A1 (en) 1998-06-26
JP2966067B2 (ja) 1999-10-25
DE69125072T2 (de) 1997-06-19
EP0474469A1 (en) 1992-03-11
DE69125072D1 (de) 1997-04-17
KR950001369B1 (ko) 1995-02-17
EP0474469B1 (en) 1997-03-12

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