KR920001329B1 - Dynamic random access momory - Google Patents

Dynamic random access momory

Info

Publication number
KR920001329B1
KR920001329B1 KR8812991A KR880012991A KR920001329B1 KR 920001329 B1 KR920001329 B1 KR 920001329B1 KR 8812991 A KR8812991 A KR 8812991A KR 880012991 A KR880012991 A KR 880012991A KR 920001329 B1 KR920001329 B1 KR 920001329B1
Authority
KR
South Korea
Prior art keywords
random access
dynamic random
access momory
momory
dynamic
Prior art date
Application number
KR8812991A
Other languages
English (en)
Other versions
KR890007288A (ko
Inventor
Hirohiko Mochizuki
Tsuyoshi Ohira
Yukinori Kodama
Meiko Kobayashi
Dakaki Furuyama
Original Assignee
Fujitsu Ltd
Fujitsu Vlsi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Vlsi Ltd filed Critical Fujitsu Ltd
Publication of KR890007288A publication Critical patent/KR890007288A/ko
Application granted granted Critical
Publication of KR920001329B1 publication Critical patent/KR920001329B1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Static Random-Access Memory (AREA)
KR8812991A 1987-10-06 1988-10-05 Dynamic random access momory KR920001329B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62-251983 1987-10-06
JP62251983A JPH0194592A (ja) 1987-10-06 1987-10-06 半導体メモリ

Publications (2)

Publication Number Publication Date
KR890007288A KR890007288A (ko) 1989-06-19
KR920001329B1 true KR920001329B1 (en) 1992-02-10

Family

ID=17230913

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8812991A KR920001329B1 (en) 1987-10-06 1988-10-05 Dynamic random access momory

Country Status (5)

Country Link
US (1) US4989182A (ko)
EP (1) EP0311047B1 (ko)
JP (1) JPH0194592A (ko)
KR (1) KR920001329B1 (ko)
DE (1) DE3882324T2 (ko)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5014242A (en) * 1987-12-10 1991-05-07 Hitachi, Ltd. Semiconductor device for a ram disposed on chip so as to minimize distances of signal paths between the logic circuits and memory circuit
USRE38379E1 (en) 1989-08-28 2004-01-06 Hitachi, Ltd. Semiconductor memory with alternately multiplexed row and column addressing
CA2028085A1 (en) * 1989-11-03 1991-05-04 Dale J. Mayer Paged memory controller
US5732035A (en) * 1990-06-14 1998-03-24 Creative Integrated Systems, Inc. Very large scale integrated planar read only memory
US5414663A (en) * 1992-07-09 1995-05-09 Creative Integrated Systems, Inc. VLSI memory with an improved sense amplifier with dummy bit lines for modeling addressable bit lines
KR930006622B1 (ko) * 1990-09-04 1993-07-21 삼성전자 주식회사 반도체 메모리장치
US5124951A (en) * 1990-09-26 1992-06-23 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with sequenced latched row line repeaters
US5502670A (en) * 1994-11-30 1996-03-26 Sony Corporation Single cycle flush for RAM memory
JPH08306773A (ja) * 1995-04-28 1996-11-22 Sharp Corp 半導体装置
US5892982A (en) * 1995-11-29 1999-04-06 Matsushita Electric Industrial Co., Ltd. External expansion bus interface circuit for connecting a micro control unit, and a digital recording and reproducing apparatus incorporating said interface circuit
US5890196A (en) * 1996-03-28 1999-03-30 Motorola, Inc. Method and apparatus for performing page mode accesses
TW522399B (en) * 1999-12-08 2003-03-01 Hitachi Ltd Semiconductor device
US6356503B1 (en) * 2000-02-23 2002-03-12 Virage Logic Corp. Reduced latency row selection circuit and method
KR100454259B1 (ko) 2001-11-02 2004-10-26 주식회사 하이닉스반도체 모니터링회로를 가지는 반도체메모리장치
US9865316B2 (en) 2016-01-21 2018-01-09 Qualcomm Incorporated Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4144590A (en) * 1976-12-29 1979-03-13 Texas Instruments Incorporated Intermediate output buffer circuit for semiconductor memory device
JPS55150189A (en) * 1979-05-10 1980-11-21 Nec Corp Memory circuit
JPS6032911B2 (ja) * 1979-07-26 1985-07-31 株式会社東芝 半導体記憶装置
JPS6012718B2 (ja) * 1980-03-28 1985-04-03 富士通株式会社 半導体ダイナミックメモリ
US4556961A (en) * 1981-05-26 1985-12-03 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory with delay means to reduce peak currents
JPS57195387A (en) * 1981-05-27 1982-12-01 Hitachi Ltd Data lien precharging system of memory integrated circuit
US4599525A (en) * 1983-02-02 1986-07-08 Rockwell International Corporation De-glitch circuitry for video game memories
JPS59185089A (ja) * 1983-04-01 1984-10-20 Hitachi Ltd 半導体記憶装置
JPS60125998A (ja) * 1983-12-12 1985-07-05 Fujitsu Ltd 半導体記憶装置
JPS6177198A (ja) * 1984-09-21 1986-04-19 Toshiba Corp 半導体記憶装置
US4710902A (en) * 1985-10-04 1987-12-01 Motorola, Inc. Technique restore for a dynamic random access memory
JPS62197990A (ja) * 1986-02-25 1987-09-01 Mitsubishi Electric Corp 半導体記憶回路

Also Published As

Publication number Publication date
DE3882324D1 (de) 1993-08-19
US4989182A (en) 1991-01-29
DE3882324T2 (de) 1994-02-17
KR890007288A (ko) 1989-06-19
JPH0194592A (ja) 1989-04-13
EP0311047A2 (en) 1989-04-12
EP0311047A3 (en) 1991-03-20
EP0311047B1 (en) 1993-07-14

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Legal Events

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E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20040120

Year of fee payment: 13

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