KR920001319A - 처리기 및 처리기의 처리방법 - Google Patents
처리기 및 처리기의 처리방법 Download PDFInfo
- Publication number
- KR920001319A KR920001319A KR1019910008872A KR910008872A KR920001319A KR 920001319 A KR920001319 A KR 920001319A KR 1019910008872 A KR1019910008872 A KR 1019910008872A KR 910008872 A KR910008872 A KR 910008872A KR 920001319 A KR920001319 A KR 920001319A
- Authority
- KR
- South Korea
- Prior art keywords
- instruction information
- operation cycle
- instruction
- data
- information data
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims 2
- 238000003672 processing method Methods 0.000 claims description 4
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 브랜칭 처리 시스템을 실행하는 동안의 처리 방법을 설명하기 위한 타이밍챠트,
제3A도는 브랜칭 처리 시스템을 실행하는 동안 인터럽트 요구가 받아들여질때 인터럽트 처리를 개시할때의 처리방법을 설명하기 위한 타이밍챠트,
제3B도는 인터럽트 처리를 종결할때의 처리방법을 설명하기 위한 타이밍 챠트.
Claims (4)
- 제1 명령정보 데이타가 일련의 동작 사이클중 제1 동작 사이클중에 인출되고 제2동작 사이클중에 제1 명령 정보 데이타에 따라서 처리가 실행됨과 동시에 제2명령 정보 데이타가 인출되는 파이프 라인 제어 방식의 처리기의 처리 방법에 있어서, 일련의 동작 사이클중에 소정 동작 사이클에서 인터럽트 요구가 있을때, 상기 동작 사이클동안 인출된 명령 정보 데이타의 어드레스 데이타 및 상기 동작 사이클에 뒤따르는 동작 사이클동안 인출된 명령 정보 데이타의 어드레스 데이타가 세이브되고, 상기 두 어드레스 데이타에 의해 지정된 명령 정보데이타는 상기 인터럽트 요구에 응답하여 실행되는 인터럽트 처리의 종료에 따라 인출되어 실행되는 것을 특징으로 하는 처리기의 방법.
- 제1 명령 정보 데이타가 일련의 동작 사이클중 제1 동작 사이클에서 인출되고 다음의 제2동작 사이클중에 제1명령 정보 데이타에 따라서 처리가 실행됨과 동시에 제2명령 정보 데이타가 인출되는 파이프 라인 제어 방식하에 동작하는 처리기에 있어서, 상기처리기는 인터럽트 요구가 일련의 동작 사이클중 소정의 동작 사이클에서 있을때 상기 동작 사이클동안 인출된 명령 정보의 어드레스 데이타와 상기 동작 사이클에 뒤따르는 명령 사이클동안 인출된 명령 정보의 어드레스 데이타를 세이브하는 시퀸서를 구비하며, 이 시퀸서는 상기 인터럽트 요구에 응답하여 실행되는 인터럽트 처리의 종료시 상기 두 어드레스 데이타에 의해 지정되는 명령 정보를 인출하여 실행하는 것을 특징으로 하는 처리기.
- 제2항에 있어서, 상기 시퀸서가 각각의 동작 사이클에 대해 증분되는 프로그램 카운터, 한 동작 사이클 동안 상기 프로그램 카운터에 의해 발생된 프로그램 어드레스 데이타를 홀드하는 제어 레지스터, 상기 프로그램 카운터에 의해 발생된 어드레스 데이타에 의해 프로그램 기억부로부터 명령 정보를 디코딩하는 처리기, 및 상기 프로그램 카운터에 의해 발생된 상기 어드레스 데이타 또는 상기 제어 레지스터에 의해 출력된 상기 어드레스 데이타를 선택하는 선택기를 구비하는 것을 특징으로 하는 처리기.
- 제3항에 있어서, 적어도 두개의 연속 정보 데이타-여기서 제2 명령에 따른 실행 상태는 제1 명령에 따른 실행 결과에 의해 제어된다-는 옥사이드 프로그램 기억부에 단일 명령 정보로서 기억되며, 상기 명령 정보 데이타 인출시 상기 시퀸서는 단일 동작 사이클내에 적어도 제1 명령 및 상기 제2명령을 실행하도록 되어 있는 특징으로 하는 처리기.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2-143883 | 1990-06-01 | ||
JP2143883A JPH0437927A (ja) | 1990-06-01 | 1990-06-01 | プロセッサの処理方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR920001319A true KR920001319A (ko) | 1992-01-30 |
Family
ID=15349242
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910008872A KR920001319A (ko) | 1990-06-01 | 1991-05-30 | 처리기 및 처리기의 처리방법 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5611061A (ko) |
EP (1) | EP0459445A3 (ko) |
JP (1) | JPH0437927A (ko) |
KR (1) | KR920001319A (ko) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0969047A (ja) * | 1995-09-01 | 1997-03-11 | Sony Corp | Risc型マイクロプロセッサおよび情報処理装置 |
US5923887A (en) * | 1996-05-20 | 1999-07-13 | Advanced Micro Devices, Inc. | Interrupt request that defines resource usage |
US6785803B1 (en) * | 1996-11-13 | 2004-08-31 | Intel Corporation | Processor including replay queue to break livelocks |
US5850556A (en) * | 1996-12-26 | 1998-12-15 | Cypress Semiconductor Corp. | Interruptible state machine |
US6751789B1 (en) | 1997-12-12 | 2004-06-15 | International Business Machines Corporation | Method and system for periodic trace sampling for real-time generation of segments of call stack trees augmented with call stack position determination |
US6732357B1 (en) | 1997-12-12 | 2004-05-04 | International Business Machines Corporation | Determining and compensating for temporal overhead in trace record generation and processing |
US6546548B1 (en) | 1997-12-12 | 2003-04-08 | International Business Machines Corporation | Method and system for compensating for output overhead in trace data using initial calibration information |
US6662358B1 (en) | 1997-12-12 | 2003-12-09 | International Business Machines Corporation | Minimizing profiling-related perturbation using periodic contextual information |
US6158024A (en) * | 1998-03-31 | 2000-12-05 | International Business Machines Corporation | Method and apparatus for structured memory analysis of data processing systems and applications |
US6513155B1 (en) | 1997-12-12 | 2003-01-28 | International Business Machines Corporation | Method and system for merging event-based data and sampled data into postprocessed trace output |
US6560773B1 (en) | 1997-12-12 | 2003-05-06 | International Business Machines Corporation | Method and system for memory leak detection in an object-oriented environment during real-time trace processing |
US6526463B1 (en) * | 2000-04-14 | 2003-02-25 | Koninklijke Philips Electronics N.V. | Dynamically selectable stack frame size for processor interrupts |
US7003543B2 (en) * | 2001-06-01 | 2006-02-21 | Microchip Technology Incorporated | Sticky z bit |
US6985986B2 (en) * | 2001-06-01 | 2006-01-10 | Microchip Technology Incorporated | Variable cycle interrupt disabling |
US6976158B2 (en) * | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Repeat instruction with interrupt |
US20030023836A1 (en) * | 2001-06-01 | 2003-01-30 | Michael Catherwood | Shadow register array control instructions |
US6934728B2 (en) * | 2001-06-01 | 2005-08-23 | Microchip Technology Incorporated | Euclidean distance instructions |
US20030028696A1 (en) * | 2001-06-01 | 2003-02-06 | Michael Catherwood | Low overhead interrupt |
US6975679B2 (en) * | 2001-06-01 | 2005-12-13 | Microchip Technology Incorporated | Configuration fuses for setting PWM options |
US7467178B2 (en) * | 2001-06-01 | 2008-12-16 | Microchip Technology Incorporated | Dual mode arithmetic saturation processing |
US6952711B2 (en) * | 2001-06-01 | 2005-10-04 | Microchip Technology Incorporated | Maximally negative signed fractional number multiplication |
US20030005268A1 (en) * | 2001-06-01 | 2003-01-02 | Catherwood Michael I. | Find first bit value instruction |
US7020788B2 (en) * | 2001-06-01 | 2006-03-28 | Microchip Technology Incorporated | Reduced power option |
US6937084B2 (en) * | 2001-06-01 | 2005-08-30 | Microchip Technology Incorporated | Processor with dual-deadtime pulse width modulation generator |
US7007172B2 (en) * | 2001-06-01 | 2006-02-28 | Microchip Technology Incorporated | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection |
US20030005269A1 (en) * | 2001-06-01 | 2003-01-02 | Conner Joshua M. | Multi-precision barrel shifting |
US20020184566A1 (en) * | 2001-06-01 | 2002-12-05 | Michael Catherwood | Register pointer trap |
US9436477B2 (en) | 2012-06-15 | 2016-09-06 | International Business Machines Corporation | Transaction abort instruction |
US9384004B2 (en) | 2012-06-15 | 2016-07-05 | International Business Machines Corporation | Randomized testing within transactional execution |
US9772854B2 (en) | 2012-06-15 | 2017-09-26 | International Business Machines Corporation | Selectively controlling instruction execution in transactional processing |
US9336046B2 (en) | 2012-06-15 | 2016-05-10 | International Business Machines Corporation | Transaction abort processing |
US8682877B2 (en) | 2012-06-15 | 2014-03-25 | International Business Machines Corporation | Constrained transaction execution |
US10437602B2 (en) | 2012-06-15 | 2019-10-08 | International Business Machines Corporation | Program interruption filtering in transactional execution |
US9448796B2 (en) | 2012-06-15 | 2016-09-20 | International Business Machines Corporation | Restricted instructions in transactional execution |
US9348642B2 (en) | 2012-06-15 | 2016-05-24 | International Business Machines Corporation | Transaction begin/end instructions |
US9740549B2 (en) | 2012-06-15 | 2017-08-22 | International Business Machines Corporation | Facilitating transaction completion subsequent to repeated aborts of the transaction |
US8688661B2 (en) | 2012-06-15 | 2014-04-01 | International Business Machines Corporation | Transactional processing |
US20130339680A1 (en) | 2012-06-15 | 2013-12-19 | International Business Machines Corporation | Nontransactional store instruction |
US9361115B2 (en) | 2012-06-15 | 2016-06-07 | International Business Machines Corporation | Saving/restoring selected registers in transactional processing |
US10642693B2 (en) * | 2017-09-06 | 2020-05-05 | Western Digital Technologies, Inc. | System and method for switching firmware |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4398244A (en) * | 1980-05-07 | 1983-08-09 | Fairchild Camera & Instrument Corporation | Interruptible microprogram sequencing unit and microprogrammed apparatus utilizing same |
US4438492A (en) * | 1980-08-01 | 1984-03-20 | Advanced Micro Devices, Inc. | Interruptable microprogram controller for microcomputer systems |
US4399507A (en) * | 1981-06-30 | 1983-08-16 | Ibm Corporation | Instruction address stack in the data memory of an instruction-pipelined processor |
US4488227A (en) * | 1982-12-03 | 1984-12-11 | Honeywell Information Systems Inc. | Program counter stacking method and apparatus for nested subroutines and interrupts |
US4498136A (en) * | 1982-12-15 | 1985-02-05 | Ibm Corporation | Interrupt processor |
DE3369015D1 (en) * | 1983-09-16 | 1987-02-12 | Ibm Deutschland | Arrangement in the command circuit of a pipe-line processor for instruction interrupt and report |
CA1250667A (en) * | 1985-04-15 | 1989-02-28 | Larry D. Larsen | Branch control in a three phase pipelined signal processor |
EP0208181A1 (en) * | 1985-06-28 | 1987-01-14 | Hewlett-Packard Company | Programme counter queue for a pipelined processor |
US4777587A (en) * | 1985-08-30 | 1988-10-11 | Advanced Micro Devices, Inc. | System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses |
US4709324A (en) * | 1985-11-27 | 1987-11-24 | Motorola, Inc. | Data processor control unit having an interrupt service using instruction prefetch redirection |
US4755935A (en) * | 1986-01-27 | 1988-07-05 | Schlumberger Technology Corporation | Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction |
US5003462A (en) * | 1988-05-31 | 1991-03-26 | International Business Machines Corporation | Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt means |
US5119483A (en) * | 1988-07-20 | 1992-06-02 | Digital Equipment Corporation | Application of state silos for recovery from memory management exceptions |
JPH0275023A (ja) * | 1988-09-09 | 1990-03-14 | Fujitsu Ltd | 遅延分岐命令における割入方式 |
US5150469A (en) * | 1988-12-12 | 1992-09-22 | Digital Equipment Corporation | System and method for processor pipeline control by selective signal deassertion |
US5185871A (en) * | 1989-12-26 | 1993-02-09 | International Business Machines Corporation | Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions |
-
1990
- 1990-06-01 JP JP2143883A patent/JPH0437927A/ja active Pending
-
1991
- 1991-05-29 EP EP19910108801 patent/EP0459445A3/en not_active Withdrawn
- 1991-05-30 KR KR1019910008872A patent/KR920001319A/ko not_active Application Discontinuation
-
1993
- 1993-11-24 US US08/158,190 patent/US5611061A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0459445A3 (en) | 1993-09-29 |
JPH0437927A (ja) | 1992-02-07 |
US5611061A (en) | 1997-03-11 |
EP0459445A2 (en) | 1991-12-04 |
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