KR910021051A - 어드레스 디코드회로 - Google Patents

어드레스 디코드회로 Download PDF

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Publication number
KR910021051A
KR910021051A KR1019910008228A KR910008228A KR910021051A KR 910021051 A KR910021051 A KR 910021051A KR 1019910008228 A KR1019910008228 A KR 1019910008228A KR 910008228 A KR910008228 A KR 910008228A KR 910021051 A KR910021051 A KR 910021051A
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KR
South Korea
Prior art keywords
logical block
channel
misfets
channel misfets
logical
Prior art date
Application number
KR1019910008228A
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English (en)
Other versions
KR940010418B1 (ko
Inventor
기요히사 구와나
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR910021051A publication Critical patent/KR910021051A/ko
Application granted granted Critical
Publication of KR940010418B1 publication Critical patent/KR940010418B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

내용 없음

Description

어드레스 디코드회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 어드레스디코드회로의 블록도.
제2도는 상기 실시예의 어드레스디코드회로에 있어서 일부분의 디코드회로의 구성을 나타낸 회로도.
제3도는 상기 실시예의 어드레스디코드회로에 있어서 어드레스신호가 3비트인 경우의 나타낸 회로도.

Claims (3)

  1. 제1채널형의 MISFET가 복수개 설치된 제1논리블럭(11)과, 제2채널형의 MISFET가 복수개 설치된 제2논리블럭(12), 상기 제1 및 제2논리블럭(11, 12)을 횡단하도록 배치되고 상기 제1 및 제2논리블럭(11, 12)내에 제1채널형 및 제2채널형 MISFET의 각 게이트에 공급할 어드레스신호를 전달하는 복수의 입력배선(13), 상기 제1 및 제2논리블럭(11, 12)의 출력을 계속 접속하는 출력배선(14)을 구비하여 구성된 것을 특징으로 하는 어드레스디코드회로.
  2. 제1항에 있어서, 상기 제1논리블럭(11)내에는 P채널 MISFET(QP1, QP2)가 복수개 설치되고, 상기 제2논리블럭(12)내에는 N채널 MISFET(QN1, QN2)가 복수개 설치된 것을 특징으로 하는 어드레스디코드회로.
  3. 제2항에 있어서, 상기 제1논리블럭(11)내에 1개의 출력에 대해서 복수개의 N채널 MISFET가 병렬접속되어 있고, 제2논리블럭(12)내에는 1개의 출력에 대해서 복수개의 N채널 MISFET가 직렬접속되어 있는 것을 특징으로 하는 어드레스디코드회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910008228A 1990-05-23 1991-05-22 어드레스디코드회로 KR940010418B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP02-131428 1990-05-23
JP2-131428 1990-05-23
JP2131428A JPH0828120B2 (ja) 1990-05-23 1990-05-23 アドレスデコード回路

Publications (2)

Publication Number Publication Date
KR910021051A true KR910021051A (ko) 1991-12-20
KR940010418B1 KR940010418B1 (ko) 1994-10-22

Family

ID=15057733

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910008228A KR940010418B1 (ko) 1990-05-23 1991-05-22 어드레스디코드회로

Country Status (3)

Country Link
US (1) US5138197A (ko)
JP (1) JPH0828120B2 (ko)
KR (1) KR940010418B1 (ko)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69324637T2 (de) * 1992-07-31 1999-12-30 Hughes Electronics Corp., El Segundo Sicherheitssystem für integrierte Schaltung und Verfahren mit implantierten Leitungen
DE4341667C1 (de) * 1993-12-07 1994-12-01 Siemens Ag Integrierte Schaltungsanordnung mit mindestens einem CMOS-NAND-Gatter und Verfahren zu deren Herstellung
US5612638A (en) * 1994-08-17 1997-03-18 Microunity Systems Engineering, Inc. Time multiplexed ratioed logic
US5783846A (en) * 1995-09-22 1998-07-21 Hughes Electronics Corporation Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering
US5973375A (en) * 1997-06-06 1999-10-26 Hughes Electronics Corporation Camouflaged circuit structure with step implants
US6396368B1 (en) 1999-11-10 2002-05-28 Hrl Laboratories, Llc CMOS-compatible MEM switches and method of making
US7217977B2 (en) 2004-04-19 2007-05-15 Hrl Laboratories, Llc Covert transformation of transistor properties as a circuit protection method
US6815816B1 (en) 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US6791191B2 (en) 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US7294935B2 (en) * 2001-01-24 2007-11-13 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
US6774413B2 (en) 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
US6740942B2 (en) 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
US6897535B2 (en) 2002-05-14 2005-05-24 Hrl Laboratories, Llc Integrated circuit with reverse engineering protection
US7049667B2 (en) * 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
AU2003293540A1 (en) 2002-12-13 2004-07-09 Raytheon Company Integrated circuit modification using well implants
JP3635374B1 (ja) * 2003-11-14 2005-04-06 有限会社Ｓｉｒｅｓ デジタル情報坦体
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL176029C (nl) * 1973-02-01 1985-02-01 Philips Nv Geintegreerde logische schakeling met komplementaire transistoren.
JPH0194636A (ja) * 1987-10-06 1989-04-13 Hitachi Ltd 半導体装置
JPH02152254A (ja) * 1988-12-02 1990-06-12 Mitsubishi Electric Corp 半導体集積回路装置

Also Published As

Publication number Publication date
KR940010418B1 (ko) 1994-10-22
US5138197A (en) 1992-08-11
JPH0428092A (ja) 1992-01-30
JPH0828120B2 (ja) 1996-03-21

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