KR910010723A - 소메모리셀 면적에서 고안정성을 갖는 반도체기억장치 - Google Patents

소메모리셀 면적에서 고안정성을 갖는 반도체기억장치 Download PDF

Info

Publication number
KR910010723A
KR910010723A KR1019900017414A KR900017414A KR910010723A KR 910010723 A KR910010723 A KR 910010723A KR 1019900017414 A KR1019900017414 A KR 1019900017414A KR 900017414 A KR900017414 A KR 900017414A KR 910010723 A KR910010723 A KR 910010723A
Authority
KR
South Korea
Prior art keywords
memory device
semiconductor memory
mosfets
memory cell
deff
Prior art date
Application number
KR1019900017414A
Other languages
English (en)
Other versions
KR0184281B1 (ko
Inventor
고이찌로 이시바시
가쯔로 사사끼
가쯔히로 시모히가시
도시아끼 야마나까
나오따까 하시모또
다까시 하시모또
아끼히로 시미즈
Original Assignee
미다 가쓰시게
가부시끼가이샤 히다찌세이사꾸쇼
오노 미노루
히다찌초 엘 에스 아이엔지니어링 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미다 가쓰시게, 가부시끼가이샤 히다찌세이사꾸쇼, 오노 미노루, 히다찌초 엘 에스 아이엔지니어링 가부시끼가이샤 filed Critical 미다 가쓰시게
Publication of KR910010723A publication Critical patent/KR910010723A/ko
Application granted granted Critical
Publication of KR0184281B1 publication Critical patent/KR0184281B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Thin Film Transistor (AREA)

Abstract

내용 없음

Description

소메모리셀 면적에서 고안정성을 갖는 반도체기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 (a)는 본 발명의 실시예의 회로도.
제1도 (b)는 본 발명의 실시예의 단면도.

Claims (4)

  1. 제1도전형의 2개의 구동 MOSFET와 2개의 전송 MOSFET로 구성된 스테이틱형 메모리셀이 반도체 기판에 형성된 반도체 기억장치에 있어서, 상기 메모리셀의 농동부하로서 제2도전형의 2개의 FET가 상기 4개의 MOSFET의 상부에 형성되고, 상기 2개의 구동 MOSFET의 채널 길이LDEFF, 채널폭 WDEFF및 상기 2개의 전송 MOSFET의 채널 길이 LTEFF, 채널 폭 WTEFF에 관하여(WDEFF/LDEFF)/(WTEFF/)LTEFF)〈3로 되는 조건이 설정되고, 상기 능동부와 FET의 전류가 1×10-8A이상으로 설정되어 있는 반도체 기억장치.
  2. 특허청구의 범위 제1항에 있어서, 상기 능동부하 FET는 폴리실리콘 TFT인 반도체 기억장치.
  3. 특허청구의 범위 제2항에 있어서, 상기 전송 MOSFET를 도통 상태로 하는 워드선의 전압 펄스의 폭 tWD,반도체 기억장치의최소사이클 시간 tcycle에 관하여 tWD〈tcycle는 조건을 설정하는 것에 의해 상기 전송 MOSFET가 비도통 상태로 되는 시간을 마련하고, 상기 비도통 상태로 되는 시간에 상기 폴리실리콘 TFT의 상기 전류에 의해서 상기 메모리셀내의 한쪽의 접속점의 충전을 실행하는 반도체 기억장치.
  4. 특허청구의 범위 제2항에 있어서, 상기 전송 MOSFET의 채널 방향과 상기 구동 MOSFET의 채널 방향이 병행인 반도체 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900017414A 1989-11-01 1990-10-30 소메모리 면적에서 고안정성을 갖는 반도체기억장치 KR0184281B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP28298489 1989-11-01
JP1-282984 1989-11-01

Publications (2)

Publication Number Publication Date
KR910010723A true KR910010723A (ko) 1991-06-29
KR0184281B1 KR0184281B1 (ko) 1999-03-20

Family

ID=17659695

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900017414A KR0184281B1 (ko) 1989-11-01 1990-10-30 소메모리 면적에서 고안정성을 갖는 반도체기억장치

Country Status (3)

Country Link
US (1) US5134581A (ko)
JP (1) JPH03218667A (ko)
KR (1) KR0184281B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724604B1 (ko) * 1999-02-10 2007-06-04 소니 가부시끼 가이샤 반도체 기억 장치

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278790A (en) * 1989-05-15 1994-01-11 Casio Computer Co., Ltd. Memory device comprising thin film memory transistors
US5350933A (en) * 1990-02-21 1994-09-27 Sony Corporation Semiconductor CMOS static RAM with overlapping thin film transistors
JPH0732200B2 (ja) * 1990-11-15 1995-04-10 株式会社東芝 スタティック型メモリセル
GB2254487B (en) * 1991-03-23 1995-06-21 Sony Corp Full CMOS type static random access memories
JPH04334054A (ja) * 1991-05-09 1992-11-20 Mitsubishi Electric Corp 半導体装置、電界効果トランジスタおよびその製造方法
US5307142A (en) * 1991-11-15 1994-04-26 The United States Of America As Represented By The United States Department Of Energy High performance static latches with complete single event upset immunity
US5264385A (en) * 1991-12-09 1993-11-23 Texas Instruments Incorporated SRAM design with no moat-to-moat spacing
US5404326A (en) * 1992-06-30 1995-04-04 Sony Corporation Static random access memory cell structure having a thin film transistor load
EP0585059B1 (en) * 1992-08-21 1999-05-12 STMicroelectronics, Inc. Vertical memory cell processing and structure manufactured by that processing
JPH06169071A (ja) * 1992-11-30 1994-06-14 Fujitsu Ltd 半導体記憶装置
JP2518133B2 (ja) * 1993-02-12 1996-07-24 日本電気株式会社 スタティック型半導体記憶装置
US5363328A (en) * 1993-06-01 1994-11-08 Motorola Inc. Highly stable asymmetric SRAM cell
US6072715A (en) * 1994-07-22 2000-06-06 Texas Instruments Incorporated Memory circuit and method of construction
JPH0869693A (ja) * 1994-08-30 1996-03-12 Mitsubishi Electric Corp スタティック型半導体記憶装置
US6028340A (en) 1995-07-10 2000-02-22 Lg Semicon Co., Ltd. Static random access memory cell having a field region
US5804477A (en) * 1997-02-24 1998-09-08 Integrated Device Technology, Inc. Method of making a 6-transistor compact static ram cell
US6519176B1 (en) * 2000-09-29 2003-02-11 Intel Corporation Dual threshold SRAM cell for single-ended sensing
US6509216B2 (en) * 2001-03-07 2003-01-21 United Microelectronics Corp. Memory structure with thin film transistor and method for fabricating the same
JP4524735B2 (ja) * 2003-06-20 2010-08-18 ルネサスエレクトロニクス株式会社 半導体記憶装置
US7436696B2 (en) * 2006-04-28 2008-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Read-preferred SRAM cell design
JP2009048772A (ja) * 2008-12-05 2009-03-05 Renesas Technology Corp 半導体記憶装置
US20160276156A1 (en) * 2015-03-16 2016-09-22 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing process thereof
US20200098934A1 (en) * 2018-09-25 2020-03-26 Shriram Shivaraman Spacer and channel layer of thin-film transistors

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4623989A (en) * 1983-08-31 1986-11-18 Texas Instruments Incorporated Memory with p-channel cell access transistors
JPH0770222B2 (ja) * 1984-06-04 1995-07-31 株式会社日立製作所 Ｍｏｓスタテイツク型ｒａｍ

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100724604B1 (ko) * 1999-02-10 2007-06-04 소니 가부시끼 가이샤 반도체 기억 장치

Also Published As

Publication number Publication date
KR0184281B1 (ko) 1999-03-20
JPH03218667A (ja) 1991-09-26
US5134581A (en) 1992-07-28

Similar Documents

Publication Publication Date Title
KR910010723A (ko) 소메모리셀 면적에서 고안정성을 갖는 반도체기억장치
KR920010900A (ko) 반도체지연회로
KR950015989A (ko) 캐패시터와 트랜지스터를 사용하는 지연 회로
KR910006732A (ko) 전류검출회로
KR910003665A (ko) 반도체 기억 회로
KR870005393A (ko) 반도체 메모리
KR960032836A (ko) 역 배터리 보호회로
KR950020014A (ko) 기준 전류 발생 회로
KR880012008A (ko) 전원절환회로
KR890005977A (ko) 증폭기 장치
KR890016759A (ko) 파워 전계 효과 트랜지스터 구동회로
EP0339962A3 (en) Field effect semiconductor device
KR890013890A (ko) 스위칭 파우워 mos 트랜지스터용 게이트 제어회로
KR880004578A (ko) 래치업 방지회로를 가진 cmos 집적회로 장치
KR940003156A (ko) 전원 공급 회로와 그 회로를 갖춘 전기 장치
KR860007753A (ko) 반도체 집전회로
KR910002116A (ko) 반도체 장치를 위한 전압 발생회로
KR900005595A (ko) 역전압으로부터 모놀리딕 구조를 보호하는 활성 다이오드
KR930015073A (ko) 반도체 장치
KR870005390A (ko) 바이플러 트랜지스터를 포함한 앰프를 가진 반도체 메모리
KR890015507A (ko) 전원전압상승검출회로
KR880004579A (ko) 래치업 방지회로를 cmos 직접회로 장치
KR890017877A (ko) Mosfet전력 스위치 장치
KR880004564A (ko) 반도체 집적회로
KR960039604A (ko) 클램프 반도체 회로

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
G170 Re-publication after modification of scope of protection [patent]
FPAY Annual fee payment

Payment date: 20091210

Year of fee payment: 12

EXPY Expiration of term