KR900013587A - 고융점금속 규화물박막을 가진 반도체장치의 제조방법 - Google Patents

고융점금속 규화물박막을 가진 반도체장치의 제조방법 Download PDF

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KR900013587A
KR900013587A KR1019900001192A KR900001192A KR900013587A KR 900013587 A KR900013587 A KR 900013587A KR 1019900001192 A KR1019900001192 A KR 1019900001192A KR 900001192 A KR900001192 A KR 900001192A KR 900013587 A KR900013587 A KR 900013587A
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manufacturing
semiconductor device
thin film
metal silicide
silicide thin
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KR1019900001192A
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KR930007440B1 (ko
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겐지 다데이와
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다니이 아끼오
마쓰시다덴끼산교오 가부시기가이샤
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Publication of KR930007440B1 publication Critical patent/KR930007440B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/003—Anneal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/909—Controlled atmosphere

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음

Description

고융점금속 규화물박막을 가진 반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도 내지 제 2e도는 각기 본 발명의 일실시예에 따른 반도체장치의 제조방법의 단계들을 나타내는 간략도.

Claims (8)

  1. 열적으로 수축할 수 있는 고융점금속규화물 박막을 가진 반도체기판을 제공하는 단계 금속규화물박막에 절연막을 형성하는 단계 및 수소를 포함하는 분위기에서 금속규화물 박막을 열처리하는 단계로 구성된 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 열처리가 바람직하게 100 내지 1000토르의 낟은 압력에서 800내지 1000℃의 온도로 수행되는 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제1항에 있어서, 상기 절연막과 규화물 박막을 원하는 형태로 패턴가공하는 단계를 더 포함하는 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제3항에 있어서, 상기 열처리가 패턴가공에 앞서 실행되는 것을 특징으로 하는 반도체장치의 제조방법.
  5. 제1항에 있어서, 상기 분위기가, 수소와 산소를 포함하는 혼합기체로 된것을 특징으로 하는 반도체장치의 제조방법.
  6. 제5항에 있어서, 수소와 산소의 혼합비율이 체적으로 0.1 지 2 :1의 범위에 있는 것을 특징으로 하는 반도체장치의 제조방법.
  7. 제1항에 있어서, 상기 금속규화물 박막이 규소화티탄 박막인 것을 특징으로 하는 반도체장치의 제조방법.
  8. 제1항에 있어서, 상기 반도체장치가 그 게이트구조의 부분으로서 고융점 금속규화물을 가진 MIS 장치이고 금속 규화물이 수소를 포함하는 분위기에서 열처리되는 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900001192A 1989-02-02 1990-02-01 고융점 금속 규소화물 박막을 가진 반도체 장치의 제조 방법 KR930007440B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP89-24190 1989-02-02
JP1-24190 1989-02-02
JP2419089 1989-02-02

Publications (2)

Publication Number Publication Date
KR900013587A true KR900013587A (ko) 1990-09-06
KR930007440B1 KR930007440B1 (ko) 1993-08-10

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KR1019900001192A KR930007440B1 (ko) 1989-02-02 1990-02-01 고융점 금속 규소화물 박막을 가진 반도체 장치의 제조 방법

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US (1) US5108953A (ko)
KR (1) KR930007440B1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09153616A (ja) * 1995-09-28 1997-06-10 Toshiba Corp 半導体装置およびその製造方法
JP3770954B2 (ja) * 1995-11-13 2006-04-26 エイ・ティ・アンド・ティ・コーポレーション 装置の製造方法
US6319804B1 (en) * 1996-03-27 2001-11-20 Advanced Micro Devices, Inc. Process to separate the doping of polygate and source drain regions in dual gate field effect transistors

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57113289A (en) * 1980-12-30 1982-07-14 Fujitsu Ltd Semiconductor device and its manufacture
US4551908A (en) * 1981-06-15 1985-11-12 Nippon Electric Co., Ltd. Process of forming electrodes and interconnections on silicon semiconductor devices
US4860086A (en) * 1983-08-30 1989-08-22 Hitachi, Ltd. Semiconductor device
FR2578272B1 (fr) * 1985-03-01 1987-05-22 Centre Nat Rech Scient Procede de formation sur un substrat d'une couche de siliciure de tungstene, utilisable notamment pour la realisation de couches d'interconnexion des circuits integres.
JPS63300566A (ja) * 1987-05-29 1988-12-07 Sharp Corp 薄膜トランジスタの製造方法

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US5108953A (en) 1992-04-28

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