KR900000912A - 반도체 집적회로 장치의 제조방법 - Google Patents

반도체 집적회로 장치의 제조방법 Download PDF

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KR900000912A
KR900000912A KR1019890007698A KR890007698A KR900000912A KR 900000912 A KR900000912 A KR 900000912A KR 1019890007698 A KR1019890007698 A KR 1019890007698A KR 890007698 A KR890007698 A KR 890007698A KR 900000912 A KR900000912 A KR 900000912A
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conductive film
manufacturing
integrated circuit
semiconductor integrated
circuit device
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KR1019890007698A
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KR0136592B1 (ko
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가즈오 야사까
유따까 시나가와
도오루 미야모또
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미다 가쓰시게
가부시끼가이샤 히다찌세이사꾸쇼
가모시따 겐이찌
히다찌 마이크로컴퓨터 엔지니어링 가부시끼가이샤
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Publication of KR900000912A publication Critical patent/KR900000912A/ko
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Publication of KR0136592B1 publication Critical patent/KR0136592B1/ko

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/383—Channel doping programmed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/34—Source electrode or drain electrode programmed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/387—Source region or drain region doping programmed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/40—ROM only having the source region and drain region on different levels, e.g. vertical channel

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체 집적회로 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 제1도에 도시한 디코더의 회로를 구성하기 위한 디코더의 셀의 평면도.
제3도는 제2도의 Ⅲ-Ⅲ선을 절단한 단면도.
제11도는 본 발명의 마이크로 ROM의 디코더 회로를 구성하는 셀을 제조공정순으로 도시한 주요부 단면도.

Claims (9)

  1. 주면을 갖고, 적어도 메모리 셀이 형성되어야 할 제1영역과 상기 메모리 셀의 정보를 리드하기 위해 디코더 회로가 형성되어야할 제2영역을 갖는 제1도전형의 반도체 기판을 준비하는 공정, 상기 제2영역의 주면상에 트루선과 바선을 갖는 상보 어드레스 신호선에서의 어드레스 신호에 따라 디코드 신호선을 선택하고, 각각이 제1도전형의 제1 MISFET와 제1도전형과는 역도전형인 제2도전형의 제2 MISFET로 구성되고, 상기 제1 및 제2 MISFET의 게이트 전극이 동일층의 제1도전막에 의해 일체로 형성되어 선택 스위치 소자의 입력단자를 구성하는 선택 스위치 소자를 여러개 형성하는 공정, 상기 선택 스위치 소자상에 그것을 덮도록 제1절연막을 형성하는 공정, 상기 입력단자상의 제1절연막의 일부를 선택적으로 제거하여 제1접속구멍을 형성하는 공정, 상기 제1절연막상에 상기 제1접속구멍을 통해서 상기 입력단자에 전기적으로 접속되고, 또한 상기 트루선 및 바선이 형성되어야 할 영역의 하부에 연장하는 제2도전막을 형성하는 공종, 상기 제2도전막상에 그것을 덮도록 제2절연막을 형성하는 공정, 상기 제2도전막상의 상기 제2절연막에 상기 제2도전막에 도달하는 제2접속구멍을 형성하는 공정, 상기 제2도전막상에 제3도전막을 형성하고, 그후 상기 제3도전막을 패터닝하는 것에 의해 상기 트루선 및 바선을 상기 제2도전막상에 형성하는 공정과 동시에 상기 트루선과 바선 중 어느 한쪽을 상기 제2접속구멍을 통해서 상기 제2도전막에 전기적으로 접속하는 공정을 구비한 반도체 집적회로 장치의 제조방법.
  2. 특허청구의 범위 제1항에 있어서, 상기 제2도전막은 제1층째의 알루미늄 배선 형성 공정에 의해 형성되는 반도체 집적회로 장치의 제조방법.
  3. 특허청구의 범위 제2항에 있어서, 상기 제3도전막은 제2층째의 알루미늄 배선 형성 공정에 의해 형성되는 반도체 집적회로 장치의 제조방법.
  4. 특허청구의 범위 제2항에 있어서, 상기 제1도전막은 상기 반도체 기판의 주면상에 마련된 다결정 실리콘막을 패터닝하는 것에 의해 형성되는 반도체 집적회로 장치의 제조방법.
  5. 특허청구의 범위 제3항에 있어서, 상기 선택 스위치 소자의 각각은 1개의 제1 MISFET와 1개의 제2 MISFET로 구성되고, 상기 디코더 회로를 구성하기 위한 1개의 셀로 되는 반도체 집적회로 장치의 제조방법.
  6. 특허청구의 범위 제5항에 있어서, 상기 제1 MISFET의 소스영역은 상기 디코더 회로의 동작전위를 공급하는 제1동작 전위 공급선에 접속되고, 상기 제1 MISFET의 드레인 영역은 상기 디코드 신호선에 접속되는 반도체 집적회로 장치의 제조방법.
  7. 특허청구의 범위 제6항에 있어서, 상기 디코드 신호선은 상기 제1층째의 알루미늄 배선 형성 공정에 의해 상기 제2도전막과 동시에 형성되는 반도체 집적회로 장치의 제조방법.
  8. 특허청구의 범위 제7항에 있어서, 상기 디코드 신호선과 상기 상보 어드레스 신호선은 서로 직교하는 방향으로 연장하는 반도체 집적회로 장치의 제조방법.
  9. 특허청구의 범위 제8항에 있어서, 상기 디코드 신호선은 상기 제1영역에 형성되어야할 메모리 셀에 접속되는 워드 선에 전기적으로 접속되는 반도체 집적회로 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890007698A 1988-06-09 1989-06-05 반도체 집적회로 장치의 제조방법 KR0136592B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63-142724 1988-06-09
JP14272488A JP2654449B2 (ja) 1988-06-09 1988-06-09 半導体集積回路装置及びその製造方法

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KR900000912A true KR900000912A (ko) 1990-01-31
KR0136592B1 KR0136592B1 (ko) 1998-09-15

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US (1) US4910162A (ko)
JP (1) JP2654449B2 (ko)
KR (1) KR0136592B1 (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06314692A (ja) * 1993-04-27 1994-11-08 Intel Corp 集積回路におけるビア／接点被覆範囲を改善する方法
JP2643901B2 (ja) * 1995-03-17 1997-08-25 日本電気株式会社 半導体装置の製造方法
JP4014708B2 (ja) * 1997-08-21 2007-11-28 株式会社ルネサステクノロジ 半導体集積回路装置の設計方法
US6795367B1 (en) * 2000-05-16 2004-09-21 Micron Technology, Inc. Layout technique for address signal lines in decoders including stitched blocks

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3970865A (en) * 1973-06-11 1976-07-20 Signetics Corporation Pseudo-complementary decode driver
US4122540A (en) * 1974-03-18 1978-10-24 Signetics Corporation Massive monolithic integrated circuit
JPS55156370A (en) * 1979-05-25 1980-12-05 Hitachi Ltd Manufacture of semiconductor device
JPH0797606B2 (ja) * 1986-10-22 1995-10-18 株式会社日立製作所 半導体集積回路装置の製造方法

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US4910162A (en) 1990-03-20
JP2654449B2 (ja) 1997-09-17
JPH021970A (ja) 1990-01-08
KR0136592B1 (ko) 1998-09-15

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