KR890013731A - 반도체 디바이스의 표면 평탄화 방법 - Google Patents

반도체 디바이스의 표면 평탄화 방법

Info

Publication number
KR890013731A
KR890013731A KR1019890002125A KR890002125A KR890013731A KR 890013731 A KR890013731 A KR 890013731A KR 1019890002125 A KR1019890002125 A KR 1019890002125A KR 890002125 A KR890002125 A KR 890002125A KR 890013731 A KR890013731 A KR 890013731A
Authority
KR
South Korea
Prior art keywords
planarizing
semiconductor devices
semiconductor
devices
Prior art date
Application number
KR1019890002125A
Other languages
English (en)
Other versions
KR0125763B1 (ko
Inventor
데 브루인 렌데르트
마르티누스 프란시스쿠스 게라르두스 반 라아르 호펜 요세푸스
Original Assignee
엔. 브이. 필립스 글로아이람펜파브리켄
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엔. 브이. 필립스 글로아이람펜파브리켄 filed Critical 엔. 브이. 필립스 글로아이람펜파브리켄
Publication of KR890013731A publication Critical patent/KR890013731A/ko
Application granted granted Critical
Publication of KR0125763B1 publication Critical patent/KR0125763B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019890002125A 1988-02-26 1989-02-23 반도체 디바이스의 표면 평탄화 방법 KR0125763B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL8802375 1988-02-26
FR8802375A FR2627902B1 (fr) 1988-02-26 1988-02-26 Procede pour aplanir la surface d'un dispositif semiconducteur

Publications (2)

Publication Number Publication Date
KR890013731A true KR890013731A (ko) 1989-09-25
KR0125763B1 KR0125763B1 (ko) 1997-12-26

Family

ID=9363670

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890002125A KR0125763B1 (ko) 1988-02-26 1989-02-23 반도체 디바이스의 표면 평탄화 방법

Country Status (5)

Country Link
EP (1) EP0336461B1 (ko)
JP (1) JP2739228B2 (ko)
KR (1) KR0125763B1 (ko)
DE (1) DE68918738T2 (ko)
FR (1) FR2627902B1 (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3801976A1 (de) * 1988-01-23 1989-08-03 Telefunken Electronic Gmbh Verfahren zum planarisieren von halbleiteroberflaechen
JP2913918B2 (ja) * 1991-08-26 1999-06-28 日本電気株式会社 半導体装置の製造方法
US5378318A (en) * 1992-06-05 1995-01-03 Vlsi Technology, Inc. Planarization
US7175773B1 (en) 2004-06-14 2007-02-13 Carl Zeiss Laser Optics Gmbh Method for manufacturing a blazed grating, such a blazed grating and a spectrometer having such a blazed grating

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59125629A (ja) * 1983-01-05 1984-07-20 Nec Corp 平担化方法
US4511430A (en) * 1984-01-30 1985-04-16 International Business Machines Corporation Control of etch rate ratio of SiO2 /photoresist for quartz planarization etch back process
NL8601694A (nl) * 1985-06-28 1987-01-16 Matsushita Electric Ind Co Ltd Werkwijze voor het vervaardigen van halfgeleider inrichtingen.
FR2587838B1 (fr) * 1985-09-20 1987-11-27 Radiotechnique Compelec Procede pour aplanir la surface d'un dispositif semi-conducteur utilisant du nitrure de silicium comme materiau isolant
US4676868A (en) * 1986-04-23 1987-06-30 Fairchild Semiconductor Corporation Method for planarizing semiconductor substrates
FR2599892B1 (fr) * 1986-06-10 1988-08-26 Schiltz Andre Procede d'aplanissement d'un substrat semiconducteur revetu d'une couche dielectrique

Also Published As

Publication number Publication date
EP0336461B1 (fr) 1994-10-12
DE68918738T2 (de) 1995-04-27
FR2627902B1 (fr) 1990-06-22
JPH01261828A (ja) 1989-10-18
JP2739228B2 (ja) 1998-04-15
KR0125763B1 (ko) 1997-12-26
EP0336461A1 (fr) 1989-10-11
DE68918738D1 (de) 1994-11-17
FR2627902A1 (fr) 1989-09-01

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