KR890008968A - 패키지 - Google Patents

패키지 Download PDF

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Publication number
KR890008968A
KR890008968A KR1019880015237A KR880015237A KR890008968A KR 890008968 A KR890008968 A KR 890008968A KR 1019880015237 A KR1019880015237 A KR 1019880015237A KR 880015237 A KR880015237 A KR 880015237A KR 890008968 A KR890008968 A KR 890008968A
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South Korea
Prior art keywords
connection
package
package according
lines
ground
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KR1019880015237A
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English (en)
Inventor
죠세프 마리 비느 미첼
세르쥬 메이그낭 디디에르
Original Assignee
이반 밀러 레르너
엔.브이.필립스 글로아이람펜파브리켄
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Publication of KR890008968A publication Critical patent/KR890008968A/ko

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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B3/00Line transmission systems
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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  • Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음

Description

패키지
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 직접회로에 관련되며 본 발명에 따른 패키지의 단면도.
제2도는 제1도의 패키지의 접속장치의 평면도.
제3a내지 3c도는 제2도의 접속장치의 단면도.

Claims (13)

  1. 집적 회로를 수용하는 리세스와 이 리세스의 주변을 따라 배열된 접촉 스터드를 갖추고 있는 하우징을 포함하는 패키지에서, 이 패키지는 하우징의 리세스내에 놓여있는 접속 장치를 더 포함하며, 상기 하우징은 집적 회로를 수용할 개구를 그것의 중앙에 갖추고 있으며 그것의 전면에서 상기 개구의 엣지로부터 그것의 주변까지 연장되는 접속 라인들을 유지하고 있는 것을 특징으로 하는 패키지.
  2. 제1항에 있어서, 접속 장치는 그것의 배면에 접지판을 형성하는 금속층을 갖추고 있는 것을 특징으로 하는 패키지.
  3. 제1 또는 2항에 있어서, 접속 장치는 적어도 50Ω의 저항을 갖고 있는 제1접속 라인들을 포함하는 것을 특징으로 하는 패키지.
  4. 제3항에 있어서, 상기 제1접속 라인들은 각각 기판의 두께와 실제로 거의 동일한 폭을 갖고 있는 유전체 판상에 놓여있는 금속 스트립을 포함하는 것을 특징으로 하는 패키지.
  5. 제2, 3 또는 4항에 있어서, 상기 접속 장치는 제1접속 라인들과 접지 사이에 연결되는 적어도 50Ω의 저항기들을 포함하는 것을 특징으로 하는 패키지.
  6. 제5항에 있어서, 상기 저항기들은 각각 양면에 접촉부를 갖추고 있는 저항층을 포함하고, 그 접촉부 중 하나는 접지에 연결되고, 다른 하나는 제1접속 라인에 연결되는 것을 특징으로 하는 패키지.
  7. 제5 또는 6항에 있어서, 제1접속 라인은 예로, 열가소성 납땜에 의해 고정되는 매우 짧은 와이어에 의해 인접 저항기의 접촉부중 하나는 연결되는 것을 특징으로 하는 패키지.
  8. 선행항중 임의 한 항에 있어서, 상기 접속 장치는 캐패시터들과 상기 캐패시터들에 의해 분리되는 제2접속 라인들을 포함하는 것을 특징으로 하는 패키지.
  9. 제8항에 있어서, 제2접속 라인은 유전체층에 의해 서로로부터 분리되어 캐패시터의 제1 및 제2전극을 각각 구성하는 제1금속층 및 제2금속층을 포함하며, 상기 제1전극은 접지에 연결되는 것을 특징으로 하는 패키지.
  10. 제8 또는 9항에 있어서, 접속 장치는 4변형이고, 제2접속 라인들은 대각선을 따라 형성되어 있는 것을 특징으로 하는 패키지.
  11. 제2 내지 9항중 임의 한 항에 있어서, 접속 라인과 접지판 사이의 접속은 금속화된 구멍 또는 반-구멍을 경유하여 이루어지는 것을 특징으로 하는 패키지.
  12. 선행항중 임의 한 항에 있어서, 접속 라인들은 짧은 와이어들에 의해 직접 회로의 한단부상에 접촉 스터드의 반대 단부상에 연결되는 것을 특징으로 하는 패키지.
  13. 선행항중 임의 한 항에 청구된 바와 같은 패키지에 사용되는 접속 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880015237A 1987-11-20 1988-11-19 패키지 KR890008968A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR8716089A FR2623662B1 (fr) 1987-11-20 1987-11-20 Dispositif de connexion pour circuits integres numeriques ultra-rapides
FR8716089 1987-11-20

Publications (1)

Publication Number Publication Date
KR890008968A true KR890008968A (ko) 1989-07-13

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KR1019880015237A KR890008968A (ko) 1987-11-20 1988-11-19 패키지

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EP (1) EP0317038A1 (ko)
JP (1) JPH01199441A (ko)
KR (1) KR890008968A (ko)
FR (1) FR2623662B1 (ko)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19625756A1 (de) * 1996-06-27 1998-01-02 Bosch Gmbh Robert Modul für ein elektrisches Gerät
DE19850915C1 (de) * 1998-11-05 2000-03-23 Bosch Gmbh Robert Monolithisch integrierte Kapazität

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0072644B1 (en) * 1981-08-14 1986-03-26 AMP INCORPORATED (a New Jersey corporation) Semiconductor chip carrier
US4551746A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation
DE3516954A1 (de) * 1984-05-14 1985-11-14 Gigabit Logic, Inc., Newbury Park, Calif. Montierte integrierte schaltung
FR2591801B1 (fr) * 1985-12-17 1988-10-14 Inf Milit Spatiale Aeronaut Boitier d'encapsulation d'un circuit electronique

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FR2623662A1 (fr) 1989-05-26
JPH01199441A (ja) 1989-08-10
FR2623662B1 (fr) 1990-03-09
EP0317038A1 (fr) 1989-05-24

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