KR890007157A - 데이타 프로세서 - Google Patents

데이타 프로세서 Download PDF

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Publication number
KR890007157A
KR890007157A KR1019880014070A KR880014070A KR890007157A KR 890007157 A KR890007157 A KR 890007157A KR 1019880014070 A KR1019880014070 A KR 1019880014070A KR 880014070 A KR880014070 A KR 880014070A KR 890007157 A KR890007157 A KR 890007157A
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South Korea
Prior art keywords
mode
communication bus
switching
instructions
data processor
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KR1019880014070A
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English (en)
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KR970011212B1 (ko
Inventor
제이.바그리카 죤
에이.하트빅슨 제이
엘.그레이 랜드
Original Assignee
빈센트 죠셉 로너
모토로라 인코포레이티드
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Application filed by 빈센트 죠셉 로너, 모토로라 인코포레이티드 filed Critical 빈센트 죠셉 로너
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G06F11/362—Software debugging
    • G06F11/3648—Software debugging using additional hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Microcomputers (AREA)

Abstract

내용 없음

Description

데이타 프로세서
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 양효한 실시예를 구비하는 집적 회로 데이타 프로세싱 시스템의 블럭 다이어그램.
제 2 도는 제 1 도의 데이타 프로세서의 프로그램 모델을 도시하는 다이어그램.
제 3 도는 제 1 도의 데이타 프로세싱 시스템의 중앙 처리 유니트의 부분 구조을 도시하는 다이어그램.

Claims (3)

  1. 병렬 통신 버스와 직렬 통신 버스를 구비하는 데이타 프로세싱 시스템용 운영의 제 1 모드 및 제 2 모드를 갖고, 제 1 모드동안 병렬 통신 버스에 의해 메모리로부터 폐치된 제 1 다수 명령을 연속적으로 수행하기 위한 제 1 수단과 제 2 모드동안 직렬 통신 인터페이스에 의해 수신되는 제 2 다수 명령을 연속적으로 수행하기 위한 제 2 수단을 구비하는 데이타 프로세서에 있어서, 운영의 제1 및 제2 모드 사이에서 스위칭 하기 위한 모드 스위치 수단과, 운영의 제 1 모드에서 운영의 제 2 모드까지 스위칭으로부터 모드 스위치 수단을 디세이블링(disabling)하기 위한 제어 수단을 구비하고 상기 모드 스위치 수단은 운영의 제 1 모드로 스위치하는 제 2다수 명령의 최소 하나에 응답하는 것을 특징으로 하는 데이타 프로세서.
  2. 병렬 통신 버스와 직렬 통신 버스를 구비하는 데이타 프로세싱 시스템용 운영의 제 1 모드 및 제 2 모드를 갖고, 제 1 모드동안 병렬 통신 버스에 의해 메모리로부터 폐치된 제 1 다수의 명령을 연속적으로 수행하기 위한 제 1 수단과 제 2 모드동안 직렬 통신 인터페이스에 의해 수신되는 제 2 다수 명령을 연속적으로 수행하기 위한 제 2 수단을 구비하는 데이타 프로세서에 있어서, 운영의 제 1 모드 제 2 모드사이에서 스위칭 하기위한 모드 스위치 수단과, 운영의 제 1 모드에서 운영의 제 2 모드까시 스위칭으로부터 모드 스위치수단을 디세이블링 하기 위한 제어 수단을 구비하고 상기 모드 스위치 수단은 운영의 제 2 모드에서 운영의 제 1 모드까지 스위치하는 데 2 다수 명령의 최소 하나에 응답하며, 운영의 제 1 모드에서 운영의 제 2 모드까지 스위치 하는 에러 상태에 응답하는 것을 특징으로 하는 데이타 프로세서.
  3. 병렬 통신 버스와 직렬 통신 버스를 구비하는 데이타 프로세싱 시스템용 운영의 제 1모드 및 제 1모드를 갖고, 제 1모드동안 병렬 통신 버스에 의해 메모리로부터 폐치된 제 1 다수의 명령을 연속적으로 수행하기 위한 제 1 수단과 제 2 모드동안 직렬 통신 인터페이스에 의해 수신되는 제 1 다수 명령을 연속적으로 수행하기 위한 제 2 수단을 구비하는 데이타 프러세서에 있어서, 운영의 제1 및 제 2 모드 사이에서 스위칭 하기 위한 모드 스위치 수단과, 운영의 제 1 모드에서 운영의 제 2 모드까지 스위칭으로부터 모든 스위치 수단을 디세이블링하기 위한 제어수단을 구비하고, 상기 모드 스위치 수단은 운영의 제 2 모드에서 운영의 제 1 모드로 스위치하는 제 2 다수의 명령의 최소 하나에 응답하고 운영의 제 1 모드에서 운영의 제 2 모드로 스위치하는 제 1 다수 명령의 최소 하나에 응답하는 것을 특징으로 하는 데이타 프로세서.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880014070A 1987-10-30 1988-10-28 데이타 프로세서 KR970011212B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/115,479 US5084814A (en) 1987-10-30 1987-10-30 Data processor with development support features
US115,479 1987-10-30

Publications (2)

Publication Number Publication Date
KR890007157A true KR890007157A (ko) 1989-06-19
KR970011212B1 KR970011212B1 (ko) 1997-07-08

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Country Status (5)

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US (1) US5084814A (ko)
EP (1) EP0313848B1 (ko)
JP (1) JPH01161448A (ko)
KR (1) KR970011212B1 (ko)
DE (1) DE3851033T2 (ko)

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EP0313848A3 (en) 1990-09-26
US5084814A (en) 1992-01-28
JPH01161448A (ja) 1989-06-26
EP0313848A2 (en) 1989-05-03
EP0313848B1 (en) 1994-08-10
DE3851033T2 (de) 1995-03-02
DE3851033D1 (de) 1994-09-15
KR970011212B1 (ko) 1997-07-08

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