KR890001196A - 반도체 및 그 제조방법 - Google Patents

반도체 및 그 제조방법 Download PDF

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KR890001196A
KR890001196A KR1019880006833A KR880006833A KR890001196A KR 890001196 A KR890001196 A KR 890001196A KR 1019880006833 A KR1019880006833 A KR 1019880006833A KR 880006833 A KR880006833 A KR 880006833A KR 890001196 A KR890001196 A KR 890001196A
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insulated gate
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KR0128501B1 (ko
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앤 피셔 캐롤
헨리 팩스만 데이비드
하비 버드 필립스
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이반 밀러 레르너
엔.브이.필립스 글로아이람펜파브리켄
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Abstract

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Description

반도체 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1내지 3도는 고압 횡 증가형 및 공핍형 IGFET를 제공하는 본 발명에 따르는 제1실시예의 각 단계를 설명하는 반도체 보디의 단면도.

Claims (16)

  1. 증가형 절연 게이트 전계효과 트랜지스터와 공핍형 절연 게이트 전계효과 트랜스터를 포함하는 반도체 제조방법에 있어서, 증가형 및 공핍형 절연 게이트전체효과 트랜지스터에, 주어진 표면에 인접한 반대 도전형의 제2영역과, 제2영역에 의해 둘러쌓이고 주어진 표면에 인접한 한 도전형의 소스 영역과 소스 영역을 향해 연장되고 주어진 표면에 인접한 비교적 낮게 도우프된 드레인 연장 영역을 가지는 한 도전형의 드레인 영역을 제공하기 위해, 반도체 보디의 주어진 표면에 인접한 한 도전형의 제1영역에 불순물을 주입시키는 단계와, 주어진 표면의 제1영역에 제1 절연 게이트를 제공하는 단계와, 주어진 표면의 제2영역에 제2절연 게이트 및 제2영역의 제1보조 영역의 채널을 덮으며, 각 소스 영역과 관련된 드레인 영역 사이에 게이트 가능한 접속을 제공하기 위하여 제2영역의 다른 제1보조 영역의 채널을 덮는 단계를 포함하며, 이 방법은 한 도전형의 채널 영역을 제2영역에 인접하여 제공하는 반대 도전형의 채널영역을 제1영역에 인접하여 제공하기 위하여 제1영역 및 제2영역에 의해 수납된 낮게 도우프된 연장부 및 제2 영역을 제공하도록 주입된 불순물의 상대적인 도우스를 독립적으로 제어하는 마스킹 수단을 사용하는 단계를 구비하는 것을 특징으로 하는 반도체 제조방법.
  2. 제1항에 있어서, 비교적 낮게 도우프된 드레인 연장 영역을 형성하도록 불순물에 제1 및 제2영역을 노출시켜서 그리고 그 이상의 단계에서 제2영역의 제1보조 영역을 형성하도록 불순물을 주입시켜서 제1 및 제2영역에의해 수납된 불순물의 상대 도우스를 독립적으로 제어하는 것을 특징으로 하는 반도체 제조방법.
  3. 제1 또는 2항에 있어서, 증가형 및 공핍형 절연 게이트 전계효과 트랜지스터에, 제1보조 영역에서 연장되는 제2영역의 다른 보조 영역을 제공하기 위해 불순물을 주입하는 단계와, 제2영역의 다른 보조 영역내에 드레인 영역과 비교적 낮게 도우프된 드레인 연장 영역을 제공하는 단계를 구비하는 것을 특징으로 하는 반도체 제조방법.
  4. 제3항에 있어서, 2이상의 단계에서 각2영역의 다른 보조 영역을 형성하도록 불순물을 주입하여 제1 및 제2영역에 의해 수납된 불순물의 상대 도우스를 독립적으로 제어하고, 제1단계후에 주어진 표면 제1 및 제2영역에 의해 수납된 불순물의 상대 도우스를 독립적으로 제어하고, 제1단계후에 주어진 표면의 제2영역을 마스킹하는 단계를 구비하는 것을 특징으로 하는 반도체 제조방법.
  5. 선행항중의 어느 한 항에 있어서, 2이상의 단계에서 절연 게이트 전계효과 트랜지스터의 비교적 낮게 도우프된 연장 영역을 형성하도록 불순물을 주입시켜서 제1 및 제2영역에 의해 수납된 불순물의 상대 도우스를 독립적으로 제어하는, 제1단계후에 주어진 표면의 제1영역을 마스킹 하는 단계를 구비하는 것을 특징으로 하는 반도체 제조방법.
  6. 제1 내지 5항에 있어서, 비교적 낮게 도우프된 드레인 연장 영역을 형성하도록 불순물의 주입을 통하여 증가 절연 게이트 전계효과 트랜지스터의 채녈 영역을 제공하도록 상기 영역을 마스킹하여 제1 및 제2 영역에 의해 수납된 불순물의 상대적인 도우스를 독립적으로 제어하는 단계를 구비하는 것을 특징으로 하는 반도체 제조방법.
  7. 선행항중의 어느 한 항에 있어서, 각 절연 게이트 전계효과 트랜지스터에 대하여, 채널 영역위의 비교적 얇은 절연층과 비교적 낮게 도우프된 드레인 연장 비교적 두꺼운 절연층을 한정하여 각 절연 게이트를 제공하고 절연물질 위에 전기도전 물질을 부착시키는 단계를 구비하는 것을 특징으로 하는 반도체 제조방법.
  8. 제7항에 있어서, 절연 게이트 전계효과 트랜지스터에 대하여, 절연층의 비교적 두꺼운 영역위의 도전층에 윈도우를 개방하여 주어진 표면에 절연 게이트를 제공한 후에 증가형 및 공핍형 IGFET의 드레인 영역을 제공하도록 불순물을 주입하고, 절연층에서 윈도우의 엣지에 걸치는 도전층의 부분을 남기도록 절연층의 비교적 두꺼운 영역에서 윈도우를 형성하도록 도전층의 윈도우를 통하여 등방성으로 절연층을 엣칭하며, 절연층에서 윈도의 엣지에 걸치는 부분을 도전층을 선택적으로 엣칭하고 절연 게이트 마스크로 사용하는 증가형 및 공핍형 절연 게이트 전계효과 트랜지스터의 드레인 영역을 제공하도록 불순물을 주입하는 단계를 구비하는 것을 특징으로 하는 반도체 제조방법.
  9. 제8항에 있어서, 비교적 두꺼운 절연층에서 윈도우를 한정하도록 비교적 두꺼운 절연물질을 습식 엣칭하고, 비교적 두꺼운 절연물질층에서 각 윈도우에 엣지에 걸쳐 있는 도전물질을 제거하도록 도전물질을 플라즈마 엣칭하는 단계는 구비하는 것을 특징으로 하는 반도체 제조방법.
  10. 제7,8 또는 9항에 있어서, 제2영역의 제1보조 영역의 비교적 깊게 도우프된 중앙 영역을 제공하도록 반대 도전형의 불순물로 주입하고 주입된 불순물을 반도체 보디에 부분적으로 확산시키며, 비교적 낮게 도우프된 드레인 연장 영역을 제공하도록 불순물을 주입하여 주어진 표면에서 비교적 두꺼운 절연물질을 성장시키고 비교적 낮게 도우프된 드레인 연장 영역과 비교적 깊게 도우프된 중앙 영역을 제공하기 위하여 반도체에 주입된 불순물 확산시키도록 산화 대기에서 반도체를 가열하는 단계를 구비하는 것을 특징으로 하는 반도체 제조방법.
  11. 제10항에 있어서, 건조한 대기에서 먼저 반도체 보디을 가열하고 습한 산화 대기에서 가열하는 단계를 구비하는 것을 특징으로 하는 반도체 제조방법.
  12. 선행항중의 한 항에 있어서, 각 IGFET에 대하여, 소스 영역으로부터 제2영역에 의해 분리되고 주어진 표면에 인접한 한 도전형의 다른 영역을 제공하도록 제2영역에 불순물 주입하고, 절연 게이트와 다른 영역 사이에 전기 접속을 제공하며 절연 게이트 전계효과 트랜지스터의 소스와 게이트 사이에 제어 다이오드를 제공하기 위해 제2영역에 소스 영역을 단락시키는 것을 특징으로 하는 반도체 제조방법.
  13. 선행항중의 한 항에 있어서, 소스 영역과 제1영역 사이에 게이트 가능한 접속을 제공하도록 보디 영역의 채널 영역 또는 제1보조 영역에 절연 게이트를 제공하기 위해 그리고 보디 영역내에 한 도전형의 소스 영역과 주어진 표면에 인접한 반대 도전형의 보디 영역을 제공하기 위해 주어진 표면의 제3영역에 불순물은 주입하도록 선행 항의 방법을 사용하여 증가형 및 공핍형 절연 게이트 전계효과 트랜지스터로에 불순물은 주입하도록 선행 항의 방법을 사용하여 증가형 및 공핍형 절연 게이트 전계효과 트랜지스터로서 종 절연 게이트 전계효과 트랜지스터를 제공하는 것을 특징으로 하는 반도체 제조방법.
  14. 반도체 보디의 주어진 표면에 인접하여 한 도전형의 제1영역과, 주어진 표면에 인접하여 반대 도전형의 제2영역을 가지는 반도체 보디를 포함하는 횡 절연 게이트 전계효과 트랜지스터로서, 제2영역은 제1보조 영역에서 연장된 비교적 낮게 도우프된 다른 보조영역과 제1보조 영역을 포함하며, 제1보조 영역에 의해 둘러쌓이고 주어진 표면에 인접한 한 도전형의 소스 영역과, 제2보조 영역에 의해 둘러 쌓이고 소스 영역과 분리되고 주어진 영역과 인접한 한 도전형의 드레인 영역과, 소스 및 드레인 영역 사이에 게이트 가능한 전기 접속을 제공하기 위해 제1보조 영역의 채널 영역에 걸쳐서 절연 게이트와 제2영역의 다른 비교기 낮게 도우프된 보조 영역내에 소스 영역을 향하여 연장되고 주진 표면에 인접한 비교적 낮게 도우프된 드레인 연장 영역을 포함하는 것을 특징으로 하는 트랜지스터.
  15. 제14항에 있어서, 제1보조 영역, 소스 및 드레인 영역은 절연 게이트에 자체 정렬되는 것을 특징으로 하는 트랜지스터.
  16. 제14 또는 15항에 있어서, 한 도전형의 다른 영역이 소스 영역으로부터 떨어지고 주어진 표면에 인접한 제2영역에 제공되며, 소스영역은 제2영역에 쇼트되고, 절연 게이트와 제2영역 사이에 제어 다이오드를 제공하도록 다른 영역과 절연 영역 사이에 전기 접속을 제공하는 것을 특징으로 하는 트랜지스터.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880006833A 1987-06-08 1988-06-08 반도체 장치 및 그 제조방법 KR0128501B1 (ko)

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JPS63312665A (ja) 1988-12-21
GB8713382D0 (en) 1987-07-15
GB2206993A (en) 1989-01-18
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