KR20180084590A - 반도체 패키지의 제조 방법 - Google Patents

반도체 패키지의 제조 방법 Download PDF

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Publication number
KR20180084590A
KR20180084590A KR1020170053562A KR20170053562A KR20180084590A KR 20180084590 A KR20180084590 A KR 20180084590A KR 1020170053562 A KR1020170053562 A KR 1020170053562A KR 20170053562 A KR20170053562 A KR 20170053562A KR 20180084590 A KR20180084590 A KR 20180084590A
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South Korea
Prior art keywords
semiconductor package
manufacturing semiconductor
wafers
tray
present
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KR1020170053562A
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English (en)
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KR101901987B1 (ko
Inventor
김남철
여용운
권용태
이영석
Original Assignee
주식회사 네패스
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Application filed by 주식회사 네패스 filed Critical 주식회사 네패스
Priority to CN201780083594.9A priority Critical patent/CN110178209B/zh
Priority to PCT/KR2017/004830 priority patent/WO2018135708A1/ko
Publication of KR20180084590A publication Critical patent/KR20180084590A/ko
Application granted granted Critical
Publication of KR101901987B1 publication Critical patent/KR101901987B1/ko
Priority to US16/505,970 priority patent/US10804146B2/en

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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Packaging Frangible Articles (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Stackable Containers (AREA)

Abstract

본 발명의 기술적 사상은 트레이에 상기 복수개의 웨이퍼들을 배치하는 단계, 상기 트레이 및 상기 복수개의 웨이퍼들 상에 인터커넥션 구조를 형성하는 단계, 및 상기 복수개의 웨이퍼들을 상기 트레이로부터 분리하는 단계를 포함하고, 상기 인터커넥션 구조를 형성하는 단계를 포함하는 반도체 패키지의 제조 방법를 제공한다.
KR1020170053562A 2017-01-17 2017-04-26 반도체 패키지의 제조 방법 KR101901987B1 (ko)

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PCT/KR2017/004830 WO2018135708A1 (ko) 2017-01-17 2017-05-10 반도체 패키지의 제조 방법
US16/505,970 US10804146B2 (en) 2017-01-17 2019-07-09 Method for producing semiconductor package

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