KR20180084588A - 반도체 패키지의 제조 방법 - Google Patents

반도체 패키지의 제조 방법 Download PDF

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Publication number
KR20180084588A
KR20180084588A KR1020170053560A KR20170053560A KR20180084588A KR 20180084588 A KR20180084588 A KR 20180084588A KR 1020170053560 A KR1020170053560 A KR 1020170053560A KR 20170053560 A KR20170053560 A KR 20170053560A KR 20180084588 A KR20180084588 A KR 20180084588A
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South Korea
Prior art keywords
semiconductor package
wafers
forming
insulation layer
manufacturing semiconductor
Prior art date
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KR1020170053560A
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English (en)
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KR101901988B1 (ko
Inventor
김남철
여용운
권용태
이영석
Original Assignee
주식회사 네패스
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Application filed by 주식회사 네패스 filed Critical 주식회사 네패스
Priority to PCT/KR2017/004825 priority Critical patent/WO2018135706A1/ko
Publication of KR20180084588A publication Critical patent/KR20180084588A/ko
Application granted granted Critical
Publication of KR101901988B1 publication Critical patent/KR101901988B1/ko
Priority to US16/505,970 priority patent/US10804146B2/en

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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device

Abstract

본 발명의 기술적 사상은 트레이에 복수개의 웨이퍼들을 배치하는 단계, 상기 복수개의 웨이퍼들 상에 상기 복수개의 웨이퍼들의 패드를 노출시키는 개구부를 가지는 제1 절연층을 형성하는 단계, 상기 제1 절연층 상에 상기 제1 절연층을 통해 노출된 상기 패드와 연결되는 시드 금속층을 형성하는 단계, 및 상기 시드 금속층 상의 적어도 하나의 지점에 도금 지그를 접촉시켜 상기 시드 금속층 상에 제1 금속층을 형성하는 단계를 포함하는 반도체 패키지의 제조 방법을 제공한다.
KR1020170053560A 2017-01-17 2017-04-26 반도체 패키지의 제조 방법 KR101901988B1 (ko)

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US16/505,970 US10804146B2 (en) 2017-01-17 2019-07-09 Method for producing semiconductor package

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111834322A (zh) * 2019-04-17 2020-10-27 Jmj韩国株式会社 半导体封装用夹具结构体及包括其的半导体封装件

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020067732A1 (ko) * 2018-09-28 2020-04-02 주식회사 네패스 반도체 패키지
JP7215206B2 (ja) * 2019-02-19 2023-01-31 富士電機株式会社 半導体装置の製造方法
CN110867386A (zh) * 2019-10-23 2020-03-06 广东芯华微电子技术有限公司 板级晶圆扇入封装方法
CN113064333A (zh) * 2021-03-19 2021-07-02 北京智创芯源科技有限公司 一种微小晶片的光刻方法、晶片载片及光刻工装
CN113793827B (zh) * 2021-09-08 2022-08-16 合肥御微半导体技术有限公司 一种晶圆承载结构及半导体检测设备
CN113891200A (zh) * 2021-09-24 2022-01-04 青岛歌尔智能传感器有限公司 一种麦克风的封装结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100887475B1 (ko) 2007-02-26 2009-03-10 주식회사 네패스 반도체 패키지 및 그 제조방법

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002097594A (ja) 2000-09-20 2002-04-02 Ebara Corp 基板めっき装置及び基板めっき方法
JP4832207B2 (ja) * 2006-08-09 2011-12-07 富士通セミコンダクター株式会社 プローバ装置用搬送トレイ
TWI478272B (zh) * 2007-08-15 2015-03-21 尼康股份有限公司 A positioning device, a bonding device, a laminated substrate manufacturing device, an exposure device, and a positioning method
KR20100077818A (ko) * 2008-12-29 2010-07-08 주식회사 동부하이텍 웨이퍼 홀더
KR101137545B1 (ko) * 2009-12-30 2012-04-20 주식회사 탑 엔지니어링 일체형 웨이퍼 트레이
JP5686570B2 (ja) * 2010-10-29 2015-03-18 株式会社ディスコ ウエーハ支持プレートの使用方法
KR20120138517A (ko) * 2011-06-15 2012-12-26 삼성전자주식회사 칩 고정 장치 및 이를 이용한 칩의 테스트 방법
US8450151B1 (en) * 2011-11-22 2013-05-28 Texas Instruments Incorporated Micro surface mount device packaging
KR101547207B1 (ko) * 2013-12-05 2015-08-25 심기준 반도체 칩의 전기적 연결 구조 및 방법
US10276541B2 (en) 2015-06-30 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package structure and methods of forming same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100887475B1 (ko) 2007-02-26 2009-03-10 주식회사 네패스 반도체 패키지 및 그 제조방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111834322A (zh) * 2019-04-17 2020-10-27 Jmj韩国株式会社 半导体封装用夹具结构体及包括其的半导体封装件
CN111834322B (zh) * 2019-04-17 2024-03-22 Jmj韩国株式会社 半导体封装用夹具结构体及包括其的半导体封装件

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KR101984929B1 (ko) 2019-06-03
US20190333809A1 (en) 2019-10-31
US10804146B2 (en) 2020-10-13
KR20180084590A (ko) 2018-07-25
CN110178209A (zh) 2019-08-27
KR101901987B1 (ko) 2018-09-27
KR101901989B1 (ko) 2018-09-27
KR101901988B1 (ko) 2018-09-27
KR20180084587A (ko) 2018-07-25
KR20180084589A (ko) 2018-07-25

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