CN110178209B - 半导体封装件的制造方法 - Google Patents

半导体封装件的制造方法 Download PDF

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Publication number
CN110178209B
CN110178209B CN201780083594.9A CN201780083594A CN110178209B CN 110178209 B CN110178209 B CN 110178209B CN 201780083594 A CN201780083594 A CN 201780083594A CN 110178209 B CN110178209 B CN 110178209B
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wafers
tray
insulating layer
forming
semiconductor package
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CN110178209A (zh
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金南澈
吕龙云
权容台
李荣锡
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Nepes Laweh Co ltd
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Nepes Laweh Co ltd
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Priority claimed from PCT/KR2017/004830 external-priority patent/WO2018135708A1/ko
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Abstract

本发明的技术思想是提供一种半导体封装件的制造方法，其包括在托盘上布置多个晶圆的步骤；在所述托盘和所述多个晶圆上形成互连结构的步骤；以及将所述多个晶圆从所述托盘分离的步骤，并包括所述形成互连结构的步骤。

Description

半导体封装件的制造方法
技术领域
本发明的技术思想涉及半导体封装件的制造方法，更具体地，涉及一种利用晶圆级封装(wafer level package)技术的半导体封装件的制造方法。
背景技术
通常，对在晶圆上通过执行各种半导体工艺而制得的半导体芯片进行半导体封装工艺以制造半导体封装件。最近，为了节约半导体封装件的生产成本，提出了一种在晶圆级上进行半导体封装工艺，并将经过半导体封装工艺的晶圆级的半导体封装件切割成半导体芯片的晶圆级封装技术。
根据晶圆级封装，由于不需要印刷电路基板(printed circuit board)，可使半导体封装件的整体厚度变薄。由于具有较薄的厚度，从而可制造出散热效果优秀的半导体封装件。然而，在利用晶圆级封装技术的过程中，需要一种能够节约半导体封装工艺的费用，且能够提高半导体封装工艺的生产效率的技术方案。
发明内容
本发明的技术思想所要解决的技术问题是提供一种能够提高半导体封装工艺的生产效率的半导体封装件的制造方法。
为了解决上述技术问题，本发明的技术思想是提供一种半导体封装件的制造方法，其包括在托盘上布置多个晶圆的步骤；所述托盘和所述多个晶圆上形成互连结构的步骤；以及将所述多个晶圆从所述托盘分离的步骤。
此外，为了解决上述技术问题，本发明的技术思想是提供一种半导体封装件的制造方法，其包括准备具有布置于第一面上的垫片的多个晶圆的步骤；准备形成有多个空腔的托盘，并且在所述多个空腔内布置所述多个晶圆以露出所述第一面的步骤；所述托盘和所述多个晶圆上形成互连结构的步骤；以及将所述多个晶圆从所述托盘分离的步骤，形成所述互连结构的步骤包括：在所述托盘及容纳于所述多个空腔的所述多个晶圆上依次形成第一绝缘层、布线层及第二绝缘层的步骤，所述第一绝缘层具有露出所述多个晶圆的垫片的开口部，所述布线层与所述多个晶圆的垫片电连接，所述第二绝缘层覆盖所述布线层；在形成所述互连结构的期间，所述多个空腔的侧壁与容纳于所述多个空腔的所述多个晶圆之间的空间由所述第一绝缘层覆盖。
根据本发明实施例涉及的半导体封装件的制造方法，由于可利用晶圆级封装技术制造半导体封装件，因此可制得小型化且散热效率优秀的半导体封装件。
进而，根据本发明的实施例涉及的半导体封装件的制造方法，由于可在托盘上布置多个晶圆，并利用面板级进行半导体封装工艺，因此可节约半导体封装工艺的费用，且可提高半导体封装工艺的生产效率。
附图说明
图1是图示本发明技术思想的部分实施例涉及的半导体封装件的制造方法的流程图。
图2a是本发明的部分实施例涉及的托盘的立体图。
图2b是沿着图2a的ⅡB-ⅡB’线的托盘的截面图，是图示在托盘上布置多个晶圆的状态的截面图。
图3是本发明技术思想的部分实施例涉及的托盘的立体图。
图4是图示本发明技术思想的部分实施例涉及的在托盘上布置多个晶圆的状态的截面图。
图5是图示本发明技术思想的部分实施例涉及的在托盘上布置多个晶圆的状态的截面图。
图6a至图6j是基于工艺顺序图示本发明技术思想的部分实施例涉及的半导体封装件的制造方法的截面图。
图7a至图7d是基于工艺顺序图示本发明技术思想的部分实施例涉及的半导体封装件的制造方法的截面图。
具体实施方式
本发明涉及的半导体封装件的制造方法包括在托盘布置多个晶圆的步骤；所述托盘及所述多个晶圆上形成互连结构的步骤；以及将所述多个晶圆从所述托盘分离的步骤，并包括所述形成互连结构的步骤。
以下，将参照附图对本发明概念的优选实施例进行详细说明。但是，本发明概念的实施例可变形为各种其他形态，不应该解释为本发明的概念范围限于以下详细说明的实施例。本发明概念的实施例应该优选解释为为了向本领域普通技术人员更加完整地说明本发明概念而提供的。相同的附图标记始终表示相同的要素。进而，附图中的各种要素和区域是概略地绘制成的。因此，本发明概念不受限于附图中绘制的相对的大小或者距离。
第一、第二等术语虽然可用于说明各种组成要素，但是所述组成要素不受限于所述术语。所述术语的使用目的在于将一个组成要素与其他组成要素区分。例如，在不超出本发明概念的权利范围的情况下，第一组成要素可命名为第二组成要素，相反地，第二组成要素可命名为第一组成要素。
本申请中使用的术语只用于说明特定的实施例，而并非用于限定本发明概念。如果单数的表述在前后文中没有明确地给出其他定义，则包括复数表述。本申请中，“包括”或者“具有”等的表述应该理解为用于指出说明书中记载的特征、数量、步骤、动作、组成要素、部件或者其组合存在，而非事先排除一个或者一个以上的其他特征、数量、动作、组成要素、部件或者其组合的存在或者附加可能性。
只要不另行定义，这里使用的所有术语包括技术术语和科学术语，具有与本发明概念所属技术领域普通技术人员的通常理解相同的含义。此外，常用的、如字典中所定义的术语应解释为在相关技术的前后文中其所指的含意，其中如果没有给出明确的定义，则不应过度地以字面上的含义进行解释。
图1是图示本发明技术思想的部分实施例涉及的半导体封装件的制造方法的流程图。
参照图1，本发明的实施例涉及的半导体封装件的制造方法依次执行准备多个晶圆的步骤(S100)，在托盘上布置多个晶圆的步骤(S200)，在多个晶圆上形成互连结构的步骤(S300)，将多个晶圆从托盘分离的步骤(S400)及分别以封装单元切割多个晶圆的步骤(S500)。
更具体地，准备多个晶圆的步骤(S100)中，准备分别包括半导体基板及在所述半导体基板上形成的半导体元件的多个晶圆。
所述半导体基板，例如，可包括硅(Si，silicon)。此外，所述半导体基板可包括如锗(Ge，germanium)的半导体元素，或者如SiC(silicon carbide)、GaAs(galliumarsenide)、InAs(indium arsenide)及InP(indium phosphide)的化合物半导体。此外，所述半导体基板可具有绝缘体上硅(SOI，silicon on insulator)结构。例如，所述半导体基板可包括埋氧层(buried oxide(BOX)layer)。所述半导体基板可包括导电区域，例如掺杂杂质的阱(well)。此外，半导体基板可具有如浅槽隔离(STI，shallow trench isolation)结构的各种元件隔离结构。
所述半导体元件可包括各种类型的多个单独元件(individual device)。例如，多个单独元件可包括各种微电子元件(microelectronic devices)，例如互补金属氧化物半导体晶体管(complementary metal-insulator-semiconductor(CMOS)transistor)等的金属氧化物半导体场效应晶体管(MOSFET，metal-oxide-semiconductor field effecttransistor)、系统LSI(large scale integration)、如CMOS图像传感器(CIS，CMOSimaging sensor)等的图像传感器、微机电系统(MEMS，micro-electro-mechanicalsystem)、有源元件、无源元件等。所述多个单独元件可与所述半导体基板的所述导电区域电连接。所述半导体元件还可包括用于电连接所述多个单独元件中至少两个，或者用于电连接所述多个单独元件和所述半导体基板的所述导电区域的导电布线或者导电插头。此外，所述多个单独元件可分别通过绝缘膜与相邻的其他单独元件电分离。
然后，在托盘上布置多个晶圆的步骤(S200)中，准备具有适合布置多个晶圆的结构的托盘(例如，参照图2a的100)，并在所述托盘的预定位置上布置多个晶圆。在部分实施例中，所述托盘形成有可容纳多个晶圆的多个空腔以便于布置多个晶圆。当在托盘的所述空腔布置晶圆时，形成有垫片的晶圆的上面朝向上部，与晶圆的上面相反的下面可与托盘的表面接触。
然后，在多个晶圆上形成互连结构的步骤(S300)中，同时对布置于托盘的多个晶圆形成互连结构。此处，互连结构(参照图6i的200)可以指为了电连接形成于晶圆的半导体元件的垫片与外部装置而形成于晶圆上的结构。所述晶圆上形成互连结构的步骤将在后序的图6b至图6h的说明部分中做出更具体地说明。
接下来，在将多个晶圆从托盘分离的步骤(S400)中，在去除通过在所述多个晶圆上形成互连结构的步骤而形成的结构的一部分之后，从托盘分离多个晶圆。从所述托盘分离的多个晶圆可以分别是包括其上部形成的互连结构的晶圆级封装形态的半导体封装件。将在稍后说明的图6i的说明部分中更具体地说明所述将多个晶圆从托盘分离的步骤。
之后，以封装单元分别切割多个晶圆的步骤(S500)，对从托盘分离的晶圆级的半导体封装件进行切割(sawing)工艺，从而可将所述晶圆级半导体封装件切割(singulation)为多个封装单元的半导体封装件。
根据本发明的实施例涉及的半导体封装件的制造方法，由于可利用晶圆级封装技术制造半导体封装件，所以可制得小型化且散热效率优秀的半导体封装件。
进而，根据本发明的实施例涉及的半导体封装件的制造方法，通过将多个晶圆布置于托盘，从而半导体封装工艺的单元工艺的至少一部分能够以面板级进行。因此，可同时对多个晶圆进行半导体封装工艺，从而可简化半导体封装工艺，而且可提高生产效率。
图2a是本发明的部分实施例涉及的托盘100的立体图。图2b是沿着图2a的ⅡB-ⅡB’线的托盘100的截面图，是图示在托盘100上布置多个晶圆10的状态的截面图。
参照图2a和图2b，托盘100具有平板(plate)形状，且可包括本体110和多个空腔120。
托盘100可具有充分大的水平面积以能够同时布置多个晶圆10。在对多个晶圆10进行半导体封装工艺的期间，托盘100可支撑多个晶圆10。如图2a所示，托盘100的外沿可具有矩形形态，但托盘100的外沿的形态并不限于此。
本体110构成托盘100的整体外观，与托盘100相同，可具有充分大的水平面积以能够同时布置多个晶圆10。
多个空腔120可提供用于可分别容纳多个晶圆10的空间。即，空腔120可以指本体110上设置的凹陷(recess)区域，可包括与晶圆10的下面相面对的底面及与晶圆10的侧部相面对的侧壁。
多个空腔120可具有与晶圆10对应的形状，例如从托盘100的上部俯视时，空腔120可具有圆形形态。图2a和图2b中多个空腔120图示为大体上具有相同的尺寸(dimensions)，但是多个空腔120的尺寸，例如多个空腔120水平面积和/或深度120h可彼此不同。进而，图2a中虽图示了形成有四个空腔120的托盘100，但一个托盘100上形成的空腔120的数量也可以是2个、3个或者5个以上。
部分实施例中，托盘100可包括缺口部130。缺口部130可分别布置于多个空腔120上，例如可布置于空腔120的侧壁。为了将晶圆10置于托盘100的预定位置上，可以布置缺口部130。通过缺口部130，晶圆10能够在空腔120内以预定方向对齐布置。在部分实施例中，缺口部130可通过与晶圆10的缺口(notch)接触并将晶圆10固定于空腔120。
在部分实施例中，托盘100可包括对齐标记140。对齐标记140可在本体110的上面111分别布置于多个空腔120的周边。为了将晶圆10置于托盘100的预定位置，可布置对齐标记140。此外，在半导体封装工艺期间，用于进行多个单元工艺的半导体制造装置可利用对齐标记140识别空腔120的位置和/或布置于空腔120上的晶圆10的位置。
如图2b所示，晶圆10可布置于空腔120内以使形成有垫片13的上面11朝向上部，使与所述上面11相反的下面与空腔120的底面相面对。换而言之，当将晶圆10布置于空腔120中时，晶圆10的活性面可向外部露出，而晶圆10的非活性面可面向空腔120的底面。空腔120的水平宽度，例如横穿空腔120的直径的水平宽度可大于晶圆10的水平宽度，由此空腔120的侧壁与晶圆10的边缘可相隔预定的距离190。可适当地调节所述空腔120的侧壁与晶圆10的边缘之间的距离190，以例如通过层叠方法在多个晶圆10和托盘100的表面上形成绝缘层(例如，参照图6b的211)时，避免所述空腔120的侧壁与晶圆10的边缘之间的空间120S被所述绝缘层填充。
部分实施例中，空腔120的深度120h实质上可与晶圆10的厚度10h相同。换而言之，当晶圆10布置于空腔120内时，本体110的上面111可具有与晶圆10的上面11相同的高度。即，本体110的上面111可位于与晶圆10的上面11相同的平面上。当本体110的上面111具有与晶圆10的上面11相同的高度时，用于覆盖本体110的上面111和晶圆10的上面11而形成的绝缘层能够形成为几乎不具有段差(stepped portion)。
本发明的实施例中，由于半导体封装件的制造过程的至少一部分以多个晶圆10布置于托盘100的状态进行，因此托盘100可由具有耐化学性和耐热性的物质构成。
部分实施例中，托盘100可由金属材料例如铁、镍、钴、钛或者包含它们的合金构成。
部分实施例中，托盘100可由陶瓷材料例如氧化铝或者碳化硅构成。
部分实施例中，托盘100可由碳纤维构成。此外，托盘100可由绝缘体的半固化片(prepreg)构成，例如托盘100可由成型之前的强化纤维等中浸透热硬化性树脂并硬化至B阶段B-stage(树脂的半硬化状态)的材料构成。
图3是本发明技术思想的部分实施例涉及的托盘100a的立体图。图3中图示的托盘100a除了多个空腔120a、120b具有相互不同的水平宽度之外，大体上具有与图2a和图2b中图示的托盘100相同的构成。图3中，与图2a和图2b相同的附图标记表示相同的部件，此处将省略或者简化其详细说明。
参照图3，托盘100a可包括具有不同水平宽度的第一空腔120a和第二空腔120b。例如，第一空腔120a的直径可大于第二空腔120b的直径。由于托盘100a包括具有不同水平宽度的第一空腔120a和第二空腔120b，因此不同直径的晶圆可同时搭载于托盘100a上。因此，可利用托盘100a对不同直径的晶圆同时进行半导体封装工艺。
附图中虽然图示了托盘100a包括具有2种水平宽度的空腔，但是也可以包括具有3种以上水平宽度的空腔。
图4是图示本发明技术思想的部分实施例涉及的在托盘100b上布置多个晶圆10的状态的截面图。图4中图示的托盘100b除了空腔120a的深度120ha之外，具有与图2a和图2b中图示的托盘100大体上相同的构成。图4中，与图2a和图2b相同的附图标记表示相同的部件，此处将省略或者简化其详细说明。
参照图4，托盘100b中具备的空腔120a的深度120ha可小于晶圆10的厚度10h。因此，当晶圆10布置于空腔120a内时，晶圆10的至少一部分可从本体110a的上面111a突出。即，当晶圆10布置于空腔120a内时，本体110a的上面111a可位于低于晶圆10的上面11的水平面上。换而言之，由空腔120a的底面至本体110a的上面111a之间的垂直距离可小于由空腔120a的底面至容纳于空腔120a的晶圆10的上面11间的垂直距离。
附图中虽未图示，但托盘100b可包括布置于空腔120a的侧壁的缺口部(参照图2a的130)和/或布置于本体110a的上面111a的对齐标记(参照图2a的140)。
当本体110a的上面111a位于低于晶圆10的上面11的水平面时，用于覆盖本体110a的上面111a和晶圆10的上面11而形成的绝缘层(例如，参照图6b的211)能够形成为在临近晶圆10的边缘的部分具有段差。此外，所述绝缘层能够形成为覆盖晶圆10的侧面的一部分。
图5是图示本发明技术思想的部分实施例涉及的在托盘100c上布置多个晶圆10的状态的截面图。图5中图示的托盘100c除了没有形成空腔之外，具有与图2a和图2b中图示的托盘100大体上相同的构成。图5中，与图2a和图2b相同的附图标记表示相同的部件，此处将省略或者简化其详细说明。
参照图5，托盘100c可提供用于布置多个晶圆10的平坦的(flat)上面111b。多个晶圆10可分别位于本体110b的上面111b的预定位置上。
附图中虽未图示，但托盘100c可包括布置于本体110b的上面111b的对齐标记(参照图2a的140)。
当托盘100c具有平坦的上面111b时，沿着托盘100c的表面和晶圆10的表面形成的绝缘层(例如，参照图6b的211)可覆盖托盘100c的上面111b，且可覆盖晶圆10的上面11和侧面的至少一部分。通过所述绝缘层，布置于托盘100c的晶圆10可在半导体封装工艺期间被固定。
图6a至图6j是基于工艺顺序图示本发明技术思想的部分实施例涉及的半导体封装件的制造方法的截面图。图6a至图6j中，将利用图2a和图2b中图示的托盘100对半导体封装件的制造方法进行说明。
参照图6a，将多个晶圆10布置于托盘100上。多个晶圆10分别可以设置成容纳于形成在托盘100上的彼此不同的空腔120中。晶圆10可布置于空腔120内以使形成有垫片13的晶圆10的上面11向上露出。换而言之，晶圆10可布置于空腔120内以使与所述上面11相反的下面与空腔120的底面相面对。换而言之，晶圆10的活性面可露出，晶圆10的非活性面可与托盘100的表面接触。
晶圆10能够以与空腔120的侧壁相隔地布置于空腔120内。由于晶圆10的侧面与空腔120的侧壁隔开，所以晶圆10的侧面与空腔120的侧壁之间可形成上部露出的空间120S。
如图6a所示，空腔120的深度可与晶圆10的厚度大体上相同，由此布置于空腔120内的晶圆10的上面11可具有与本体110的上面111相同的水平高度。
然而，并不限于此，当晶圆10布置于空腔120内时，本体110的上面也可以具有不同于晶圆10的上面11的水平高度。例如，本体110的上面可具有低于晶圆10的上面11的水平面。
参照图6b，在托盘100和多个晶圆10上形成第一绝缘层211。所述第一绝缘层211上可形成有开口部211H，所述开口部211H可以使垫片13的至少一部分露出。第一绝缘层211可覆盖本体110的上面111和多个晶圆10的上面11。
第一绝缘层211在后续工艺期间可执行用于固定布置在空腔120内的晶圆10的功能。此外，第一绝缘层211可覆盖晶圆10与空腔120的侧壁之间的空间120S。例如，晶圆10与空腔120的侧壁之间的空间120S可用第一绝缘层211密封。第一绝缘层211在形成互连结构的期间可通过覆盖晶圆10与空腔120的侧壁之间的空间120S，来防止杂质流入所述空间120S。
部分实施例中，第一绝缘层211可形成为覆盖晶圆10的侧面与空腔120的侧壁之间的所述空间120S的上部，但晶圆10的侧面与空腔120的侧壁之间的空间120S可能不被构成第一绝缘层211的物质填充。由于构成第一绝缘层211的物质未填充到晶圆10的侧面与空腔120的侧壁之间的空间120S中，因此可便于以后将晶圆10从托盘100分离。
部分实施例中，第一绝缘层211可通过利用绝缘膜的成膜工艺而形成。更具体地，为了形成第一绝缘层211，通过层叠方法将感光薄膜附接于本体110的上面111和多个晶圆10的上面11之后，可通过曝光和显影工艺去除所述感光薄膜的一部分以露出晶圆10的垫片。
此外，部分实施例中，第一绝缘层211可包括非感光性物质。例如，为了形成第一绝缘层211，将非感光膜附接于本体110的上面111和多个晶圆10的上面11之后，可利用激光切割装置去除所述非感光薄膜的一部分以露出晶圆10的垫片。
第一绝缘层211，例如可由聚酰亚胺(polyimide)等的聚合物物质构成。
另外，另一实施例中，第一绝缘层211也可以通过旋涂法(spin-coating)形成。
参照图6c，形成用于覆盖第一绝缘层211的表面及用于覆盖通过第一绝缘层211的开口部211H露出的垫片13的表面的籽晶金属层221a。虽然可通过例如溅镀方法涂覆所述籽晶金属层221a，但籽晶金属层221a的形成方法并不限于此。籽晶金属层221a可包括例如Ti、Cu、Ni、Al、Pt、Au、Ag、W、Ta、Co或者其组合中任意一个。
参照图6d，在籽晶金属层221a上形成具有第一掩模开口部290H的第一掩模图案290。籽晶金属层221a的一部分可通过第一掩模开口部290H露出。
例如，在籽晶金属层221a上形成感光性物质膜之后，对所述感光性物质膜进行利用光刻法技术的图案化工艺，从而可形成第一掩模图案290。为了进行光刻法工艺，可使用形成有预定图案的曝光掩模，可使用KrF或者ArF等的激光光源。
部分实施例中，第一掩模图案290可通过成膜工艺形成。例如，在为了覆盖籽晶金属层221a而将感光薄膜附接于籽晶金属层221a上之后，可通过曝光和显影工艺形成使籽晶金属层221a的一部分露出的第一掩模开口部290H。
参照图6e，形成用于填充第一掩模开口部290H的至少一部分的第一金属层223。第一金属层223能够形成为覆盖通过第一掩模开口部290H露出的籽晶金属层221a部分的表面。
第一金属层223可通过例如镀金方法而形成。例如，第一金属层223可由铜构成。部分实施例中，第一金属层223可通过将籽晶金属层221a作为籽晶(seed)并利用镀金方法而形成。例如，第一金属层223可通过浸镀(immersion plating)、无电式电镀(electrolessplating)、电镀(electro plating)或者其组合而形成。
部分实施例中，形成于托盘100的上面111和多个晶圆10上的籽晶金属层221a可形成为整体上具有大体上均匀的厚度。尤其，当空腔120的深度与容纳于空腔120的晶圆10的厚度实质上相同时，空腔120的侧壁与容纳于空腔120的晶圆10之间的空间(参照图6b的120)附近的籽晶金属层221a可以没有段差。这种情况下，在空腔120的侧壁与容纳于空腔120的晶圆10之间的空间附近，籽晶金属层211a可与托盘100的上面111平行。此外，空腔120的侧壁与容纳于空腔120的晶圆10之间的空间上的籽晶金属层221a部分的厚度可与多个晶圆10上的籽晶金属层221a部分的厚度实质上相同。由此，在利用镀金夹具(省略图示)向籽晶金属层221a施加电源方式的镀金工艺中，所述电源可更加均匀地供给到整个籽晶金属层221。例如，即使使所述镀金夹具与托盘100的上面111的边缘附近的籽晶金属层221a的一个点接触，通过所述镀金夹具施加的电源也能够整体均匀地供给到具有均匀厚度的籽晶金属层211a。
参照图6f，形成第一金属层223之后，从图6e的结果物中去除第一掩模图案290及第一掩模图案290下面的籽晶金属层(图6e的221a)部分。
为了去除第一掩模图案290，可利用灰化(ashing)或者剥除(strip)工艺。此外，去除第一掩模图案290之后，可利用化学蚀刻方法去除第一掩模图案290下面的籽晶金属层(图6e的221a)部分。
部分实施例中，可将所述第一金属层223和籽晶金属层221一体结合，并且可构成布线层220(distribution layer)。
参照图6g，形成覆盖第一金属层223的第二绝缘层213，接下来依次形成贯通第二绝缘层213并连接到第一金属层223的第二金属层225。部分实施例中，第一绝缘层211、布线层220、第二绝缘层213及第二金属层225可构成互连结构200a。
部分实施例中，第二绝缘层213可以以与参照图6b说明的第一绝缘层211类似的方式通过成膜工艺形成。第二绝缘层213可包括感光性物质，而且还可以包括非感光性物质。
部分实施例中，第二金属层225可以是凸点下金属(under bump metal，UBM)。其他实施例也可省略第二金属层225。
参照图6h，第二金属层225上形成外部连接端子400。外部连接端子400，例如可以是焊球或者焊接凸点。外部连接端子400可被构造为将半导体封装件与外部装置电连接。外部连接端子400可通过籽晶金属层221、第一金属层223及第二金属层225与晶圆10的垫片13电连接。另外，当省略第二金属层225时，外部连接端子400可附接到通过第二绝缘层213露出的第一金属层223上。
参照图6i，为了将多个晶圆10从托盘100分离，可去除层叠于托盘100和/或多个晶圆10上的结构物的一部分。此时，还可以去除空腔120的侧壁与容纳于空腔120的晶圆10之间残留的物质。
例如，通过去除托盘100上和/或多个晶圆10上层叠的结构物的一部分，互连结构200上可形成分离道250(separation lane)。所述分离道250可垂直贯通第一绝缘层211和第二绝缘层213，并且可分别沿着多个晶圆10的边缘部分形成。从上面俯视时所述分离道250可为环状。通过分离道250可使空腔120的侧壁与晶圆10的边缘之间的空间120S向上部露出。进而，还可露出晶圆10的边缘区域的一部分和/或托盘100的表面的一部分。包括晶圆10与晶圆10上部的互连结构200的多个晶圆级的半导体封装件可通过分离道250相互分离。
分离道250例如可通过激光打孔方法形成。
参照图6j，将晶圆级的半导体封装件1从托盘分离，并通过切割工艺将晶圆级的半导体封装件1切割(singulation)为多个封装单元的半导体封装件。换而言之，切割叶片(BL)可通过沿着划线(scribe lane，SL)进行切割，来将晶圆级的半导体封装件1分离。其结果，晶圆级的半导体封装件1可切割为多个封装单元的半导体封装件。
图7a至图7d是基于工艺顺序图示本发明技术思想的部分实施例涉及的半导体封装件的制造方法的截面图。图7a至图7d中，将说明利用图5图示的托盘100c的半导体封装件的制造方法，并且将省略或者简化其说明与参照图6a至图6j说明的部分重复的部分。
参照图7a，将多个晶圆10布置于托盘100c上。多个晶圆10可分别使形成有垫片13的上面11向上部露出，并且使与所述上面11相反的下面面向托盘100c的表面。为了将多个晶圆10布置于托盘100c上的预定位置上，可利用布置于托盘100c上的对齐标记(参照图2a的140)。
参照图7b，形成第一绝缘层311，所述第一绝缘层311可覆盖托盘100c的表面和晶圆10的表面，并具有露出晶圆10的垫片13的开口部311H。由于晶圆10的上面11具有高于托盘100c的表面的水平面，因此第一绝缘层311能够形成为具有段差。第一绝缘层311在后续的工艺期间可将多个晶圆10固定于托盘100c上预定位置。
参照图7c，进行与图6c至图6g中说明的实质上相同的过程之后，在多个晶圆10和托盘100c上形成互连结构300a，并形成用于与第二金属层325连接的外部连接端子400。
参照图7d，为了将多个晶圆10从托盘100c分离，可沿着多个晶圆10的边缘去除第一绝缘层311的一部分和第二绝缘层313的一部分。
由于沿着多个晶圆10的边缘去除第一绝缘层311的一部分和第二绝缘层313的一部分，互连结构300上可形成分离道350。包括晶圆10与晶圆10上部互连结构300的多个晶圆级的半导体封装件可通过分离道350相互分离。
形成分离道350之后，可将所述晶圆级的半导体封装件从托盘100c分离。分离的晶圆级半导体封装件可分别通过切割工艺切割为多个封装单元的半导体封装件。
根据本发明的实施例涉及的半导体封装件的制造方法，半导体封装工艺的多个单元工艺可利用能够支撑多个晶圆的托盘来进行。即，由于半导体封装工艺通过将多个晶圆布置于托盘来进行，因此能够以面板级制造多个晶圆级的半导体封装件。因此，根据本发明的技术思想，可对多个晶圆同时进行半导体封装工艺，因此可提高生产效率。
如上所述，通过附图和说明书公开了示例性实施例。本说明书中虽使用特定的术语对实施例进行了说明，但这只是用于说明本公开的技术思想，并非用于限定其含义或权利要求书中记载的本公开的范围。因此，对于本技术领域技术人员而言，应该能够理解基于此可进行各种变形及实施等同的其他实施例。因此，本公开的实质技术保护范围应取决于附上的权利要求书的技术思想。

Claims (13)

1.一种半导体封装件的制造方法，其特征在于，包括：
在托盘上布置多个晶圆的步骤；
在所述托盘和所述多个晶圆上形成互连结构的步骤；以及
将所述多个晶圆从所述托盘分离的步骤，
所述形成互连结构的步骤包括：形成第一绝缘层的步骤，所述第一绝缘层覆盖所述托盘上的所述多个晶圆且具有露出布置于所述多个晶圆的上面的垫片的开口部；以及在所述第一绝缘层上形成布线层的步骤，
所述第一绝缘层包括与所述托盘的表面接触的第一部分、与所述多个晶圆接触的第二部分及在所述第一部分与所述第二部分之间延伸的第三部分，
所述第三部分隔着第一空间与所述多个晶圆相隔，所述第三部分在形成所述布线层的期间覆盖所述第一空间。
2.如权利要求1所述的半导体封装件的制造方法，其特征在于，
所述托盘具有可容纳所述多个晶圆的多个空腔，
在形成所述互连结构的期间，所述多个晶圆分别容纳于所述托盘的所述多个空腔。
3.如权利要求2所述的半导体封装件的制造方法，其特征在于，
在所述布置多个晶圆的步骤中，容纳于所述多个空腔的所述多个晶圆的上面的水平面等于或者低于所述托盘的上面的水平面。
4.如权利要求1所述的半导体封装件的制造方法，其特征在于，
在所述形成第一绝缘层的步骤中，所述第一绝缘层覆盖所述托盘的表面及所述多个晶圆的表面以固定布置于所述托盘的所述多个晶圆。
5.如权利要求1所述的半导体封装件的制造方法，其特征在于，
所述形成互连结构的步骤包括：
在所述形成布线层的步骤之后，形成覆盖所述布线层的第二绝缘层的步骤；以及
去除所述第二绝缘层的一部分以露出所述布线层的一部分的步骤。
6.如权利要求5所述的半导体封装件的制造方法，其特征在于，
所述形成布线层的步骤包括：
在所述第一绝缘层的表面和所述多个晶圆的垫片的表面上形成籽晶金属层的步骤；以及
利用镀金方法在所述籽晶金属层的一部分上形成第一金属层的步骤。
7.如权利要求1所述的半导体封装件的制造方法，其特征在于，
将所述多个晶圆从所述托盘分离的步骤包括去除所述第一绝缘层的一部分以露出所述多个晶圆的边缘的步骤。
8.如权利要求1所述的半导体封装件的制造方法，其特征在于，
所述托盘包括对齐标记，所述对齐标记布置于所述托盘的上面以使所述多个晶圆位于所述托盘上的预定位置。
9.一种半导体封装件的制造方法，其特征在于，包括：
准备具有布置于第一面上的垫片的多个晶圆的步骤；
准备形成有多个空腔的托盘，并且在所述多个空腔内布置所述多个晶圆以露出所述第一面的步骤；
在所述托盘和所述多个晶圆上形成互连结构的步骤；以及
将所述多个晶圆从所述托盘分离的步骤，
所述形成互连结构的步骤包括
在所述托盘及容纳于所述多个空腔的所述多个晶圆上依次形成第一绝缘层、布线层及第二绝缘层的步骤，所述第一绝缘层覆盖所述空腔的侧壁与收容于所述空腔的所述晶圆的侧面之间的第一空间且具有露出所述多个晶圆的垫片的开口部，所述布线层与所述多个晶圆的垫片电连接，所述第二绝缘层覆盖所述布线层，
在形成所述互连结构的期间，所述第一空间由所述第一绝缘层覆盖。
10.如权利要求9所述的半导体封装件的制造方法，其特征在于，
所述形成第一绝缘层的步骤中，在所述托盘及容纳于所述多个空腔的所述多个晶圆上附接感光薄膜，并通过曝光和显影工艺去除所述感光薄膜的一部分以露出所述多个晶圆的垫片。
11.如权利要求9所述的半导体封装件的制造方法，其特征在于，
将所述多个晶圆从所述托盘分离的步骤中，沿着所述多个晶圆的边缘去除所述第一绝缘层的一部分及所述第二绝缘层的一部分，以使所述所述第一空间露出。
12.如权利要求9所述的半导体封装件的制造方法，其特征在于，
所述形成布线层的步骤包括：
形成覆盖所述第一绝缘层且与通过所述第一绝缘层露出的所述多个晶圆的垫片接触的籽晶金属层的步骤；
在所述籽晶金属层上形成具有露出所述籽晶金属层的一部分的掩模开口部的掩模图案的步骤；
在所述籽晶金属层上形成第一金属层以填充所述掩模开口部的至少一部分的步骤；以及
去除所述掩模图案及所述掩模图案下面的所述籽晶金属层部分的步骤，
在所述形成籽晶金属层的步骤中，覆盖所述第一空间的所述籽晶金属层的部分与所述托盘的上面平行。
13.如权利要求9所述的半导体封装件的制造方法，其特征在于，
所述托盘包括布置于所述多个空腔的侧壁的缺口部，
在所述布置多个晶圆的步骤中，利用所述缺口部将所述多个晶圆布置于所述多个空腔内以使所述多个晶圆以预定方向对齐。
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US8450151B1 (en) 2011-11-22 2013-05-28 Texas Instruments Incorporated Micro surface mount device packaging
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