SG10201907327RA - Redistribution substrate, method of fabricating the same, and semiconductor package including the same - Google Patents
Redistribution substrate, method of fabricating the same, and semiconductor package including the sameInfo
- Publication number
- SG10201907327RA SG10201907327RA SG10201907327RA SG10201907327RA SG10201907327RA SG 10201907327R A SG10201907327R A SG 10201907327RA SG 10201907327R A SG10201907327R A SG 10201907327RA SG 10201907327R A SG10201907327R A SG 10201907327RA SG 10201907327R A SG10201907327R A SG 10201907327RA
- Authority
- SG
- Singapore
- Prior art keywords
- same
- fabricating
- semiconductor package
- package including
- redistribution substrate
- Prior art date
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Applications Claiming Priority (1)
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KR1020180109695A KR102542573B1 (en) | 2018-09-13 | 2018-09-13 | A redistribution substrate, a method for manufacturing the same, and a semiconductor package including the same |
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SG10201907327RA true SG10201907327RA (en) | 2020-04-29 |
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SG10201907327RA SG10201907327RA (en) | 2018-09-13 | 2019-08-07 | Redistribution substrate, method of fabricating the same, and semiconductor package including the same |
Country Status (4)
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US (3) | US10950539B2 (en) |
KR (1) | KR102542573B1 (en) |
CN (1) | CN110896062B (en) |
SG (1) | SG10201907327RA (en) |
Families Citing this family (4)
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KR102542573B1 (en) | 2018-09-13 | 2023-06-13 | 삼성전자주식회사 | A redistribution substrate, a method for manufacturing the same, and a semiconductor package including the same |
US11682630B2 (en) | 2020-07-31 | 2023-06-20 | Samsung Electronics Co., Ltd. | Semiconductor package |
US11183446B1 (en) * | 2020-08-17 | 2021-11-23 | Qualcomm Incorporated | X.5 layer substrate |
KR20220025545A (en) | 2020-08-24 | 2022-03-03 | 삼성전자주식회사 | semiconductor package for improving reliablity |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7381642B2 (en) * | 2004-09-23 | 2008-06-03 | Megica Corporation | Top layers of metal for integrated circuits |
KR100298827B1 (en) * | 1999-07-09 | 2001-11-01 | 윤종용 | Method For Manufacturing Wafer Level Chip Scale Packages Using Redistribution Substrate |
WO2001063991A1 (en) * | 2000-02-25 | 2001-08-30 | Ibiden Co., Ltd. | Multilayer printed wiring board and method for producing multilayer printed wiring board |
KR20050010262A (en) | 2003-07-18 | 2005-01-27 | 매그나칩 반도체 유한회사 | Method of forming metal line in semiconductor device |
JP4686962B2 (en) | 2003-07-18 | 2011-05-25 | カシオ計算機株式会社 | Manufacturing method of semiconductor device |
SG139753A1 (en) * | 2004-03-15 | 2008-02-29 | Yamaha Corp | Semiconductor device |
JP2005310841A (en) * | 2004-04-16 | 2005-11-04 | Sony Corp | Circuit module body and manufacturing method thereof |
US7582556B2 (en) | 2005-06-24 | 2009-09-01 | Megica Corporation | Circuitry component and method for forming the same |
US7902660B1 (en) * | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
TWI370515B (en) * | 2006-09-29 | 2012-08-11 | Megica Corp | Circuit component |
CN101226889B (en) | 2007-01-15 | 2010-05-19 | 百慕达南茂科技股份有限公司 | Reconfiguration line structure and manufacturing method thereof |
JP4668938B2 (en) | 2007-03-20 | 2011-04-13 | Okiセミコンダクタ株式会社 | Semiconductor device and manufacturing method thereof |
JP4881211B2 (en) * | 2007-04-13 | 2012-02-22 | 新光電気工業株式会社 | Wiring substrate manufacturing method, semiconductor device manufacturing method, and wiring substrate |
JPWO2009113198A1 (en) * | 2008-03-14 | 2011-07-21 | イビデン株式会社 | Interposer and method of manufacturing interposer |
JP5291485B2 (en) | 2009-02-13 | 2013-09-18 | ラピスセミコンダクタ株式会社 | Manufacturing method of semiconductor device |
JP2011171614A (en) | 2010-02-22 | 2011-09-01 | Casio Computer Co Ltd | Semiconductor device, and method of manufacturing the same |
JP2013030593A (en) * | 2011-07-28 | 2013-02-07 | J Devices:Kk | Semiconductor devices, semiconductor module structure formed by vertically laminated semiconductor devices, and manufacturing method of semiconductor module structure |
WO2013062593A1 (en) | 2011-10-28 | 2013-05-02 | Intel Corporation | 3d interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias |
JP2013214578A (en) * | 2012-03-30 | 2013-10-17 | Ibiden Co Ltd | Wiring board and method for manufacturing the same |
JP6142499B2 (en) * | 2012-10-23 | 2017-06-07 | 富士通株式会社 | Wiring structure and manufacturing method thereof |
US8846548B2 (en) * | 2013-01-09 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Post-passivation interconnect structure and methods for forming the same |
US9559044B2 (en) * | 2013-06-25 | 2017-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with solder regions aligned to recesses |
CN105814679A (en) | 2013-06-28 | 2016-07-27 | 英特尔公司 | Preservation of fine pitch redistribution lines |
CN205016513U (en) | 2014-10-24 | 2016-02-03 | 胡迪群 | Circuit is distribution layer structure again with encapsulation colloid supports |
KR101743467B1 (en) | 2015-08-24 | 2017-06-07 | 주식회사 에스에프에이반도체 | Method for manfacturing fan-out type wafer level package |
US10304700B2 (en) | 2015-10-20 | 2019-05-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method |
KR102579880B1 (en) | 2016-05-12 | 2023-09-18 | 삼성전자주식회사 | Interposer, semiconductor package, and method of fabricating interposer |
US20170338128A1 (en) | 2016-05-17 | 2017-11-23 | Powertech Technology Inc. | Manufacturing method of package structure |
TWI590350B (en) | 2016-06-30 | 2017-07-01 | 欣興電子股份有限公司 | Method for manufacturing circuit redistribution structure and circuit redistribution structure unit |
US10276548B2 (en) | 2016-09-14 | 2019-04-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages having dummy connectors and methods of forming same |
JP6773518B2 (en) | 2016-10-24 | 2020-10-21 | 新光電気工業株式会社 | Wiring board and its manufacturing method and electronic component equipment |
CN108022896A (en) | 2016-11-01 | 2018-05-11 | 财团法人工业技术研究院 | Chip packaging structure and manufacturing method thereof |
US10424539B2 (en) * | 2016-12-21 | 2019-09-24 | Advanced Semiconductor Engineering, Inc. | Wiring structure, semiconductor package structure and semiconductor process |
US10763206B2 (en) * | 2017-10-30 | 2020-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating integrated fan-out packages |
US11062915B2 (en) * | 2018-03-29 | 2021-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Redistribution structures for semiconductor packages and methods of forming the same |
KR102542573B1 (en) * | 2018-09-13 | 2023-06-13 | 삼성전자주식회사 | A redistribution substrate, a method for manufacturing the same, and a semiconductor package including the same |
KR102597994B1 (en) * | 2018-12-06 | 2023-11-06 | 삼성전자주식회사 | Connection structure and method of forming the same |
KR20220033636A (en) * | 2020-09-09 | 2022-03-17 | 삼성전자주식회사 | Semiconductor package |
-
2018
- 2018-09-13 KR KR1020180109695A patent/KR102542573B1/en active IP Right Grant
-
2019
- 2019-03-13 US US16/351,709 patent/US10950539B2/en active Active
- 2019-08-07 SG SG10201907327RA patent/SG10201907327RA/en unknown
- 2019-09-09 CN CN201910845973.8A patent/CN110896062B/en active Active
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2021
- 2021-03-02 US US17/189,964 patent/US11600564B2/en active Active
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2023
- 2023-02-06 US US18/105,945 patent/US11973028B2/en active Active
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US10950539B2 (en) | 2021-03-16 |
CN110896062B (en) | 2024-04-26 |
US11600564B2 (en) | 2023-03-07 |
US20200091066A1 (en) | 2020-03-19 |
US20210183766A1 (en) | 2021-06-17 |
KR20200031202A (en) | 2020-03-24 |
US20230187345A1 (en) | 2023-06-15 |
US11973028B2 (en) | 2024-04-30 |
CN110896062A (en) | 2020-03-20 |
KR102542573B1 (en) | 2023-06-13 |
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